Implementing 5G NR Features in FPGA

Bishop, James M.; Chareau, Jean-Marc; Bonavitacola, Fausto

doi:10.1109/eucnc.2018.8443214

Cited by 12 publications

(4 citation statements)

References 3 publications

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“…The basic design does not come with any signal processing implemented on a Spartan 6 LX150T FPGA, and based on the user requirement, some processing done in software can be offloaded to the FPGA. In [14], physical layer features of 5G NR were implemented using National Instruments Communications LTE Application Framework, and tests involving transmission/reception of a 4K video have been performed.…”

Section: Related Workmentioning

confidence: 99%

Real Time Receiver Baseband Processing Platform for Sub 6 GHz PHY Layer Experiments

Handagala

Leeser

2020

IEEE Access

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Wireless communication is rapidly evolving to fulfill diverse requirements in a number of application areas. Researchers are experimenting with novel ideas to improve different aspects of communication systems and performance metrics. While computer simulation is the first step to validating these approaches, testing platforms are needed to transform them to implementations for further validation and experimentation. Software Defined Radios (SDR) and System on Chip (SoC) offer a great deal of flexibility and versatility allowing researchers to experiment with wireless algorithms. However there are challenges; noise, channel effects, and synchronization errors have to be dealt with, and measures to mitigate their effects on received symbols should be implemented. Existing research using state of the art SDR platforms has not leveraged the powerful processing capabilities of Field Programmable Gate Arrays (FPGAs) in SoCs for receiver backend operations. In this work, we use high level tools to describe hardware, and automatically synthesize and implement receiver baseband wireless signal processing algorithms for FPGA targets. We demonstrate the ability to use such platforms for real world applications using over the air waveforms. We use Xilinx ZC706, Zedboard, ADI's FMComms3, and NXP's BGA7210 variable gain amplifier (VGA) for the experiments presented in this paper. Use cases considered include testing the performance of higher order modulation schemes, adjacent channel interference, power amplifier (PA) gain compression and effects on the bit error rate (BER) performance.

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Section: Related Workmentioning

confidence: 99%

Real Time Receiver Baseband Processing Platform for Sub 6 GHz PHY Layer Experiments

Handagala

Leeser

2020

IEEE Access

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“…However, none of these works consider 3GPP compatible 5G PHY. The work in [26] is limited to OFDM-based transceivers but does not consider various control and data channels in 5G while the work in [49] is limited to software-based CS implementation using USRP. In this work, we design software and hardware IP cores of 3GPP compatible 5G PHY and demonstrate the 5G CS operations by developing the receiver PHY.…”

Section: Review: Mapping Of 5g Cs Phy On Hardwarementioning

confidence: 99%

“…Deep learning for CS may not be suitable for low latency applications [24]. Other blocks of the CS physical layer (PHY), including message generators, channel encoders, data modulators, scramblers, interleaves, and their counterparts in the receivers, are redesigned in 5G [25,26]. Thus, efficient design of 5G CS and in-depth performance analysis are essential to understand computational complexity and identify the limitations for future standard releases.…”

Section: Introductionmentioning

confidence: 99%

Design and Performance Analysis of Hardware Realization of 3GPP Physical Layer for 5G Cell Search

Lodhi,

Chhillar,

Darak

et al. 2023

Chips

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5G Cell Search (CS) is the first step for user equipment (UE) to initiate communication with the 5G node B (gNB) every time it is powered ON. In cellular networks, CS is accomplished via synchronization signals (SS) broadcasted by gNB. 5G 3rd generation partnership project (3GPP) specifications offer a detailed discussion on the SS generation at gNB, but a limited understanding of their blind search and detection is available. Unlike 4G, 5G SS may not be transmitted at the center of carrier frequency, and their frequency location is unknown to UE. In this work, we demonstrate the 5G CS by designing 3GPP compatible hardware realization of the physical layer (PHY) of the gNB transmitter and UE receiver. The proposed SS detection explores a novel down-sampling approach resulting in a 60% reduction in on-chip memory and 50% lower search time. Via detailed performance analysis, we analyze the functional correctness, computational complexity, and latency of the proposed approach for different word lengths, signal-to-noise ratio (SNR), and down-sampling factors. We demonstrate end-to-end 5G CS using GNU Radio-based RFNoC framework on the USRP-FPGA platform and achieve 66% faster SS search compared to software. The 3GPP compatibility and demonstration on hardware strengthen the commercial significance of the proposed work.

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“…The flexibility, energy efficiency, and parallel processing capabilities make FPGAs an ideal choice for the efficient implementation of 5G NR (New Radio) functions. As early as now, we witness the results of these studies in works [1][2][3][4][5], where the implementation of certain 5G NR functions on FPGAs is comprehensively described. This not only demonstrates the relevance of using FPGAs in this field but also underscores their ability to adapt to the requirements of high-speed data processing and parallel processing.…”

Section: Introductionmentioning

confidence: 97%

Implementation of Functional Block Radio Unit Based on System-on-Chip

Ibraimov

2023

Eurasian phys. tech. j.

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This article discusses the implementation of the Radio Unit functional block based on the System-on-Chip. The primary focus was on integrating Radio Unit blocks such as modulation and Fast Fourier Transform on Field-Programmable Gate Array. Technical aspects of design, module testing, and Radio Unit block performance optimization are thoroughly examined. The results demonstrate that when separating the functionality of the 7.3 technology Fifth Generation (5G) radio block, the modulation module uses the minimum Field-Programmable Gate Array resources compared to other blocks. The Fast Fourier Transform block can meet delay requirements at the maximum Field-Programmable Gate Array size and clock frequency of 250 MHz. This article serves as a resource for engineers and researchers interested in optimizing the development and integration process of high-performance functional blocks in modern radio systems.

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Implementing 5G NR Features in FPGA

Cited by 12 publications

References 3 publications

Real Time Receiver Baseband Processing Platform for Sub 6 GHz PHY Layer Experiments

Real Time Receiver Baseband Processing Platform for Sub 6 GHz PHY Layer Experiments

Design and Performance Analysis of Hardware Realization of 3GPP Physical Layer for 5G Cell Search

Implementation of Functional Block Radio Unit Based on System-on-Chip

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