Implementing a Highly Parameterized Digital PIV System on Reconfigurable Hardware

Abstract

This paper presents PARPIV the design and prototyping of a highly parameterized digital Particle Image Velocimetry (PIV) system implemented on reconfigurable hardware. Despite many improvements to PIV methods over the last twenty years, PIV post-processing remains a computationally intensive task. It becomes a serious bottleneck as camera acquisition rates reach 1000 frames per second. In this research, we aim to substantially speed up PIV processing by implementing it in reconfigurable hardware. Furthermore, this implementation is highly parameterized, supporting adaptation to a variety of setups and application domains. The circuit is parameterized by the dimensions of the captured images as well as the dimensions of the interrogation windows and sub-areas, pixel representation, board memory width, displacement and overlap. Through this work a parameterized library of different VHDL components was built. To the best of the authors' knowledge, this is the first highly parameterized PIV system implemented on reconfigurable hardware reported in the literature. For a typical PIV configuration with images of 512 512 pixels, 40 40 pixel interrogation windows and 32 32 pixel sub-areas, we achieved about 65\ times speedup in hardware over a standard software implementation.

Kernel Specialization Provides Adaptable GPU Code for Particle Image Velocimetry

“…The PIV kernels are also compared to previously optimized FPGA implementations [15], [16]. In addition, KS and RE kernel performance are compared.…”