Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture

Ebeling, Carl; Fisher, Chris; Xing, Guanbin; Shen, Manyuan; Liu, Hui

doi:10.1007/978-3-540-45234-8_3

Cited by 15 publications

(17 citation statements)

References 3 publications

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“…Both types of dependences impose a set of distances by which the nodes must be separated in the flat schedule in order to have identical execution to the one described in the initial loop specification. The distance imposed by a single dependence edge (λ u , δ u,v ) ∈ E * is given in (6), while the distance by a single input dependence edge (δ Ru,v ) ∈ E * R is given in (7). The scheduler exploits these distances in the algorithm of Fig.…”

Section: Scheduling Loopmentioning

confidence: 99%

“…Many CGRA architectures have been proposed in the past few years [1][2][3][4][5][6][7] accompanied with an equal number of mapping methodologies. The work in [4] combines a RISC processor with a reconfigurable 8 × 8 array (subdivided into 4 quadrants) of identical 16-bit PEs.…”

Section: Related Workmentioning

confidence: 99%

“…Coarse-Grained Reconfigurable Array (CGRA) architectures [1][2][3][4][5][6][7] have been proposed for accelerating time consuming loops in applications that realize computations over a large set of data. In many recent works [3,4,8], CGRAs have been integrated as hardware accelerators in System On Chips (SOCs) with Instruction Set Processors (ISP).…”

Section: Introductionmentioning

confidence: 99%

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Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays

et al. 2008

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Coarse Grain Reconfigurable Array (CGRA) architectures have been extensively used for accelerating time consuming loops. The design of such systems requires good balance between the architecture abilities and the loops' characteristics. A reliable design is characterized by optimized cost-performance trade-off. The main target of this paper is to present an exploration framework that automates the evaluation of CGRA architectures. In specific, the framework helps the designer to identify CGRA architectures tuned toward a specific application domain. The whole process is assisted: (1) by an optimized retargetable compiler based on modulo scheduling and (2) by the Synopsys Design Compiler that provides realization metrics such as the area and clock frequency. Both target on the description of a parametric CGRA architecture template which is capable of instantiating a large diversity of these architectures. Until now, many studies suggest that clock frequency influences performance. However, none of them examines the impact of architecture on clock frequency and performance. Our work studies in a unified way for the first time the area, the clock frequency, the instructions per cycle and performance. Hence, architectures with good compromise between cost and performance can be identified. Another objective of the paper is to present the advances made to the compiler approach used by the exploration framework. In specific, a new more effective priority scheme is proposed while the modulo scheduler has been equipped with backtracking capability. The experiments outline the algorithm's efficiency and scalability for a given set of DSP benchmarks. Moreover, optimized architectures with respect to cost-performance trade-off have been identified by an exploration over 72 CGRA architecture alternatives.

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Section: Scheduling Loopmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays

et al. 2008

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“…For instance, RaPiD (Reconfigurable Pipelined Datapath) [11] is a coarse grain reconfigurable architecture organized as a linear array of functional units. It provides a reconfigurable-pipelined datapath controlled by efficient reconfigurable control logic.…”

Section: Related Workmentioning

confidence: 99%

The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform

Grasset¹,

Millet²,

Bonnot³

et al. 2010

Int J Parallel Prog

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Reconfigurable computing offers a wide range of low cost and efficient solutions for embedded systems. The proper choice of the reconfigurable device, the granularity of its processing elements and its memory architecture highly depend on This work was supported in part by the European Union in the 6th R&D Framework Program (MORPHEUS IST project, number 027342).A. Grasset (B) · P. Millet · P. Bonnot · S. Yehia 329 the type of application and their data flow. Existing solutions either offer fine grain FPGAs, which rely on a hardware synthesis flow and offer the maximum degree of flexibility, or coarser grain solutions, which are usually more suitable for a particular type of data flow and applications. In this paper, we present the MORPHEUS architecture, a versatile reconfigurable heterogeneous System-on-Chip targeting streaming applications. The presented architecture exploits different reconfigurable technologies at several computation granularities that efficiently address the different applications needs. In order to efficiently exploit the presented architecture, we implemented a complete software solution to map C applications to the reconfigurable architecture. In this paper, we describe the complete toolset and provide concrete use cases of the architecture.

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“…Area and power consumption are important design parameters in embedded systems. Additionally, coarse-grained reconfigurable hardware [18,19] can be used as coprocessor. However, research activities, as the one in [19], showed that an ASIC solution outperforms this type of reconfigurable logic in both performance and area.…”

Section: Related Workmentioning

confidence: 99%

Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path

Galanis

Dimitroulakos

Goutis

2007

J Sign Process Syst Sign Image

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The speedups and the energy reductions achieved in a generic single-chip microprocessor system by employing a high-performance data-path are presented. The data-path acts as a coprocessor that accelerates computational intensive kernel sections thereby increasing the overall performance. The authors have previously introduced the data-path which is composed by flexible computational components (FCCs). These components can realize any two-level sequence of primitive operations. The automated coprocessor synthesis method from high-level software description and its integration to a design flow for executing applications on the system is presented. The overall application speedups of eleven real-life applications, relative to the software execution on the microprocessor, are estimated using the design flow. These speedups are close to theoretical bounds and range from 1.78 to 5.84, having an average value of 3.04, while the overhead in circuit area is small. The energy savings range from 41 to 74%, while the reduction in the application energy-delay product has an average value of 80%. A comparison with another high-performance data-path showed that the proposed coprocessor achieves better performance, consumes less energy and has smaller area-time products for the generated data-paths. Additionally, the FCC data-path achieves better performance in accelerating kernels relative to a VLIW DSP core.

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Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture

Cited by 15 publications

References 3 publications

Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays

Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays

The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform

Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path

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