Implementing dynamic implied addressing mode for multi-output instructions

Youn, Jonghee M.; Lee, Jongwon; Paek, Yunheung; Kim, Jongwung; Cho, Jeonghun

doi:10.1145/1878921.1878937

Cited by 2 publications

(3 citation statements)

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“…In [37], Youn et al introduced a mechanism that can conceal the overhead of executing ROA instructions in a single-issue RISC architecture. The idea is relatively simple.…”

Section: Related Workmentioning

confidence: 99%

“…Normally a reduced bit-width instruction set contains only a small subset of the original instruction set due to the reduced encoding space. However, using Dynamic Implied Addressing Mode (DIAM) [37] excessive information that cannot be encoded within the reduced bit-width, such as a register number or an immediate value, can be specified as a separate instruction, and at runtime dynamically combined with the matching instruction. This hardware-assisted approach allows for 100% equivalent behavior as the original instruction sequence, while providing important benefits such as code size reduction (41% on average) and reduced energy consumption (8 ∼ 16% on average) on a 4-way VLIW processor for a set of compute-intensive kernels [19].…”

Section: Introductionmentioning

confidence: 99%

“…Such performance degradation is aggravated in loops as opposed to straight-line code, since in loops extra instructions are more likely to generate extra VLIW packets. While simply upping the average instruction fetch rate may be enough to negate the effect of extra instructions in the case of a single-issue processor [37], the changes made to VLIW packets by extra instructions are more permanent and much harder to reverse at runtime. In this paper to address the runtime overhead we present a revised DIAM-based instruction encoding scheme for VLIW processors.…”

Section: Introductionmentioning

confidence: 99%

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Improving performance of loops on DIAM-based VLIW architectures

Lee

et al. 2014

Proceedings of the 2014 SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems

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Recent studies show that very long instruction word (VLIW) architectures, which inherently have wide datapath (e.g. 128 or 256 bits for one VLIW instruction word), can benefit from dynamic implied addressing mode (DIAM) and can achieve lower power consumption and smaller code size with a small performance overhead. Such overhead, which is claimed to be small, is mainly caused by the execution of additionally generated special instructions for conveying information that cannot be encoded in reduced instruction bit-width. In this paper, however, we show that the performance impact of applying DIAM on VLIW architecture cannot be overlooked expecially when applications possess high level of instruction level parallelism (ILP), which is mostly the case for loops because of the result of aggressive code scheduling. We also propose a way to relieve the performance degradation especially focusing on loops since loops spend almost 90% of total execution time in programs and tend to have high ILP. We first implement the original DIAM compilation technique in a compiler, and augment it with the proposed loop optimization scheme to show that ours can clearly alleviate the performance loss caused by the excessive number of additional instructions, with the help of slightly modified hardware. Moreover, the well-known loop unrolling scheme, which would produce denser code in loops at the cost of substantial code size bloating, is integrated into our compiler. The experiment result shows that the loop unrolling technique, combined with our augmented DIAM scheme, produces far better code in terms of performance with quite an acceptable amount of code increase.

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“…In [37], Youn et al introduced a mechanism that can conceal the overhead of executing ROA instructions in a single-issue RISC architecture. The idea is relatively simple.…”

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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