Implementing OpenSHMEM for the Adapteva Epiphany RISC Array Processor

Abstract

The energy-efficient Adapteva Epiphany architecture exhibits massive many-core scalability in a physically compact 2D array of RISC cores with a fast network-on-chip (NoC). With fully divergent cores capable of MIMD execution, the physical topology and memory-mapped capabilities of the core and network translate well to partitioned global address space (PGAS) parallel programming models. Following an investigation into the use of two-sided communication using threaded MPI, one-sided communication using SHMEM is being explored. Here we present work in progress on the development of an OpenSHMEM 1.2 implementation for the Epiphany architecture.

Software-Distributed Shared Memory over Heterogeneous Micro-server Architecture

“…Software-Distributed Shared Memory has become popular in the late eighties [11] with the introduction of systems for computing clusters [5,6,2,3], followed by systems for computing grids [4,12] and many-core processors [14]. These S-DSM are designed for a particular architecture and reasonably expect the same performance from the physical resources.…”

A Distributed Shared Memory Model and C++ Templated Meta-Programming Interface for the Epiphany RISC Array Processor

“…The availability of the inexpensive Adapteva Parallella platform with the 16-core Epiphany-III processor has led to several investigations of the architecture and various programming models. We have recently published results for threaded MPI [7], an OpenSHMEM programming model for Epiphany [8] [9] and other advances in runtime performance and interoperability [11]. To date, no prior publications have reported on the evaluation of the Epiphany architecture using an object-based software DSM model or high-level C++ TMP techniques for parallel programming.…”

“…A 16-core Epiphany-III processor [5] has been integrated into the Parallella mini-computer platform [6] where the RISC array is supported by a dual-core ARM CPU and asymmetric shared-memory access to off-chip global memory. We have recently published results for threaded MPI [7], an OpenSHMEM programming model for Epiphany [8][9], a hybrid programming model [10], and other advances in runtime performance and interoperability [11].RISC array processors, such as those based on the Epiphany architecture, may offer significant computational power efficiency in the near future with requirements in increased core counts, including long-term plans for exascale platforms. The power efficiency of the Epiphany architecture has been specifically identified as both a guide and prospective architecture for such platforms [12].…”

On the Performance and Isolation of Asymmetric Microkernel Design for Lightweight Manycores

“…The rationale for this observation emerges from the system-level support for these processors. So far, several solutions that run at the runtime level were introduced to ease programmability of lightweight manycores, such as OpenMP, Partitioned Global Address Space (PGAS) and Message Passing Interface (MPI) [10], [11]. However, these solutions do no effectively enable resource sharing and multiplexing; and they lack on providing rich abstractions.…”