Implementing time-predictable load and store operations

Abstract

Scratchpads have been widely proposed as an alternative to caches for embedded systems. Advantages of scratchpads include reduced energy consumption in comparison to a cache and access latencies that are independent of the preceding memory access pattern. The latter property makes memory accesses time-predictable, which is useful for hard real-time tasks as the worst-case execution time (WCET) must be safely estimated in order to check that the system will meet timing requirements.However, data must be explicitly moved between scratchpad and external memory as a task executes in order to make best use of the limited scratchpad space. When dynamic data is moved, issues such as pointer aliasing and pointer invalidation become problematic. Previous work has proposed solutions that are not suitable for hard real-time tasks because memory accesses are not time-predictable. This paper proposes the scratchpad memory management unit (SMMU) as an enhancement to scratchpad technology. The SMMU implements an alternative solution to the pointer aliasing and pointer invalidation problems which (1) does not require whole-program pointer analysis and (2) makes every memory access operation time-predictable. This allows WCET analysis to be applied to hard-real time tasks which use a scratchpad and dynamic data, but results are also applicable in the wider context of minimizing energy consumption or average execution time. Experiments using C software show that the combination of an SMMU and scratchpad compares favorably with the best and worst case performance of a conventional data cache.

A Predictable Execution Model for COTS-Based Embedded Systems

“…Instead of a standard cache-based architecture, a real-time scratchpad architecture can be used to provide predictable access time to main memory [28]. The Precision Time (PRET) machine [4] promises to simultaneously deliver high computational performance together with cycle-accurate estimation of program execution time.…”

WCET-aware dynamic code management on scratchpads for Software-Managed Multicores

“…We check the cost of the temporary mapping (line 14) and keep a record of the best two regions to be merged (line [15][16][17][18]. After trying all combinations, we update the current mapping by merging the best pair of regions (line [19][20][21] …”

“…When n is 1, this is the same as the model for a single core by Whitham et al [21]. We take the most conservative way of considering the inference of other cores, i.e., multiplying the cost of a single core by the number of cores.…”

“…We keep a record of the best combination of a function to be moved, bf , and the new region for it, br (line [15][16][17][18][19]. After trying all functions, we update the current mapping by moving function bf to region br (line [21][22]. br being greater than nr means that we just made a new region, so we increase the number of regions (line [23][24].…”

Data cache organization for accurate timing analysis

“…Whitham and Audsley propose a special form of SPM, which includes scratchpad memory management unit (SMMU) [53,55]. The SMMU is in charge to redirect pointers into the SPM when data is moved into the SPM.…”