Implicit vs. explicit resource allocation in SMT processors

Cazorla, Francisco J.; Knijnenburg, Peter M. W.; Sakellariou, Rizos; Fernandez, E.; Ramirez, A.; Valero, Mateo

doi:10.1109/dsd.2004.1333257

Cited by 8 publications

(6 citation statements)

References 21 publications

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“…The main problem of using SMT processors in real-time systems is that in an SMT processor threads share almost all hardware resources. This may may cause interference between threads which implies that the speed a thread obtains in one workload can be very different from the speed it has in another workload [4]. In contrast to previous approaches, our methods do not require any knowledge beyond information that is traditionally used by the OS level job scheduler, namely, Worst Case Execution Time and the Period of the time-critical thread.…”

Section: Discussionmentioning

confidence: 99%

See 1 more Smart Citation

Architectural support for real-time task scheduling in SMT processors

Cazorla

Knijnenburg

Sakellariou

et al. 2005

Proceedings of the 2005 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

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In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architectures suitable for use in embedded systems. However, since threads share many resources, like caches, they also interfere with each other. As a result, execution times of applications become highly unpredictable and highly dependent on the context in which an application is executed. Obviously, this poses problems if an SMT is to be used in a (soft) real time system. In this paper, we propose two novel hardware mechanisms that can be used to reduce this performance variability. In contrast to previous approaches, our proposed mechanisms do not need any information beyond the information already known by traditional job schedulers. Neither do they require extensive profiling of workloads to determine optimal schedules. Our mechanisms are based on dynamic resource partitioning. The OS level job scheduler needs to be slightly adapted in order to provide the hardware resource allocator some information on how this resource partitioning needs to be done. We show that our mechanisms provide high stability for SMT architectures to be used in real time systems: the real time benchmarks we used meet their deadlines in more than 98% of the cases considered while the other thread in the workload still achieves high throughput.

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Section: Discussionmentioning

confidence: 99%

“…This implies that the speed a thread obtains in one workload can be very different from the speed it has in another workload [4]. We refer to this by saying that an SMT processor has a high variability.…”

Section: Introductionmentioning

confidence: 99%

Architectural support for real-time task scheduling in SMT processors

Cazorla

Knijnenburg

Sakellariou

et al. 2005

Proceedings of the 2005 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

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show abstract

“…The primary thread will only receive an equal share of the computing resources, but the overall throughput of one core reaches the maximum. Next, we use our PGPA framework and set a high target IPC (2.0) to enforce the primary thread to use the highest priority value (6). The results show that the IPC of the primary threads increases for all cases.…”

Section: B Effectivenessmentioning

confidence: 93%

“…Improving code execution efficiency is another challenge [6], [7]. For example, it is desirable to allocate less resource to the system idle process.…”

Section: A Software-adjustable Thread Priority In Power Processorsmentioning

confidence: 99%

PMU-guided Priority Adjustment to Guarantee Thread Performance on IBM POWER SMT Processor

Hong

2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

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Simultaneous-multithreading (SMT) is widely used to improve the overall efficiency of superscalar CPUs with hardware multi-threading. With SMT processors, it is challenging to guarantee the performance of each individual thread because resources are shared across the threads. In this paper, we study the scenario where user applications need to guarantee a certain level of performance for a primary thread. We present a hardware-software integrated method to control thread priority to achieve this objective. This method combines hardware thread priority control (which is currently available on IBM POWER processor series) and performance monitoring unit, and dynamically adjusts CPU resource allocations according to current thread workloads. Effectiveness of the proposed method is demonstrated through extensive experimental results.

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“…To deal with these problems, a new class of MT processors have been proposed in the literature. These proposals allow Explicit Resource Allocation (ERA) [15], where the OS can specify or bias the hardware resource sharing to meet specific targets.…”

Section: Background On Resource Allocationmentioning

confidence: 99%

Exploring coordinated software and hardware support for hardware resource allocation

Boneti¹

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Multithreaded processors are now common in the industry as they offer high performance at a low cost. Traditionally, in such processors, the assignation of hardware resources between the multiple threads is done implicitly, by the hardware policies. However, a new class of multithreaded hardware allows the explicit allocation of resources to be controlled or biased by the software. Currently, there is little or no coordination between the allocation of resources done by the hardware and the prioritization of tasks done by the software.<br/>This thesis targets to narrow the gap between the software and the hardware, with respect to the hardware resource allocation, by proposing a new explicit resource allocation hardware mechanism and novel schedulers that use the currently available hardware resource allocation mechanisms.<br/>It approaches the problem in two different types of computing systems: on the high performance computing domain, we characterize the first processor to present a mechanism that allows the software to bias the allocation hardware resources, the IBM POWER5. In addition, we propose the use of hardware resource allocation as a way to balance high performance computing applications. Finally, we propose two new scheduling mechanisms that are able to transparently and successfully balance applications in real systems using the hardware resource allocation. On the soft real-time domain, we propose a hardware extension to the existing explicit resource allocation hardware and, in addition, two software schedulers that use the explicit allocation hardware to improve the schedulability of tasks in a soft real-time system.<br/>In this thesis, we demonstrate that system performance improves by making the software aware of the mechanisms to control the amount of resources given to each running thread. In particular, for the high performance computing domain, we show that it is possible to decrease the execution time of MPI applications biasing the hardware resource assignation between threads. In addition, we show that it is possible to decrease the number of missed deadlines when scheduling tasks in a soft real-time SMT system.

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Implicit vs. explicit resource allocation in SMT processors

Abstract: In a Simultaneous Multithreaded (SMT)

Cited by 8 publications

References 21 publications

Architectural support for real-time task scheduling in SMT processors

Architectural support for real-time task scheduling in SMT processors

PMU-guided Priority Adjustment to Guarantee Thread Performance on IBM POWER SMT Processor

Exploring coordinated software and hardware support for hardware resource allocation

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