Importance Boundary Sampling for SRAM Yield Analysis With Multiple Failure Regions

Yao, Jian; Ye, Zuochang; Wang, Yan

doi:10.1109/tcad.2013.2292504

Cited by 19 publications

(5 citation statements)

References 22 publications

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“…One major route to tackle the issue is based on the importance sampling [4][5][6][7][8][9][10][11][12][13][14][15]. The aim is to construct the distorted probability density function (PDF) which can generate sample data in the failure region with high probability.…”

Section: Introductionmentioning

confidence: 99%

“…The aim is to construct the distorted probability density function (PDF) which can generate sample data in the failure region with high probability. The optimal distorted PDF is usually circuit-specific and difficult to construct in practice [5], therefore, most existing approaches tried to generate samples in regions where failure events most likely happen. The minimized normalization importance sampling (MN-IS) searched the most probable failure points (MPFP) to construct optimal shift vectors (OSV).…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Equiprobability-Based Local Response Surface Method for High-Sigma Yield Estimation With Both High Accuracy and Efficiency

Liu

Ren

Chen

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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With the ever-increasing transistor density and memory capability in integrated circuits, the high-sigma yield estimation has become a growing concern. This work presents an equiprobability-based local response surface method (ELRS) that can perform high-sigma yield estimation with both high accuracy and efficiency. Demonstrating with 6T-SRAM, the proposed method exhibits more than 10 times improvement in accuracy when comparing with the state-of-the-art while maintaining the efficiency to the best record in literature.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Equiprobability-Based Local Response Surface Method for High-Sigma Yield Estimation With Both High Accuracy and Efficiency

Liu

Ren

Chen

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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show abstract

“…In [8]- [11], the SRAM operation yield is estimated by boundary searching (BS). The BS methods determine the boundaries of the failure regions in the circuit parameter variation space.…”

Section: Introductionmentioning

confidence: 99%

High-Density SRAM Read Access Yield Estimation Methodology

Baek

Jeong

2021

IEEE Access

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As high-density SRAMs must be designed to ensure a substantially small failure rate, the accurate yield estimation with practically acceptable runtime of circuit simulations is highly challenging. Here, a read access yield estimation method for high-density static random access memory (SRAM) is proposed. Instead of performing SPICE runs for the entire SRAM circuit, the proposed method partitions the SRAM into three parts-the control signal generation circuit, bitcell array, and sense amplifier (SA)that determine three key parameters: word-line to SA enable delay, bit-line voltage difference, and SA offset voltage. Subsequently, the proposed method derives the probability density of these key parameters from each of the three partitioned circuits. Here, different methods are applied to derive the probability of the key parameters, considering the respective characteristics of each circuit part and parameter. According to our experimental results, the proposed method can accelerate the yield estimation by 500-3000×, compared with the brute-force Monte Carlo simulation method, and 10-100× compared with the other state-of-art methods. In addition, the proposed method can accelerate the circuit optimization procedure accompanied by multiple circuit revisions, that is, the circuit revisions can be reflected with SPICE runs only for the revised circuit part, unlike the previous methods that require SPICE runs for the entire SRAM.INDEX TERMS Process variation, read access yield, sensing yield, static random access memory (SRAM), yield estimation.

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“…Most of existing acceleration methods are based on the importance sampling methods [1]- [3]. More recent methods are based on importance sampling plus surrogate modeling [4] [5], and this reduces the number of SPICE simulation to a few thousand or less, enabling yield analysis for SRAMs with acceptable effort.…”

Section: Introductionmentioning

confidence: 99%

Yield driven design and optimization for near-threshold voltage SRAM cells

Chen

Wang

2016

2016 China Semiconductor Technology International Conference (CSTIC)

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Production yield of SRAM cells is a key bottleneck for supply voltage scaling in low power circuits. Yielddriven design for such circuits are difficult as yield analysis for such circuits are usually very expensive. In this paper we proposed a hybrid performance model that can map the process parameters as well as design parameters to performance metric such as SNM, WNM and read/write speed. Once trained, such model allows extremely fast evaluation of production yield without the need to perform expensive circuit simulations. Thus it is very useful for design parameter screening and automatic optimization.

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Importance Boundary Sampling for SRAM Yield Analysis With Multiple Failure Regions

Cited by 19 publications

References 22 publications

Equiprobability-Based Local Response Surface Method for High-Sigma Yield Estimation With Both High Accuracy and Efficiency

Equiprobability-Based Local Response Surface Method for High-Sigma Yield Estimation With Both High Accuracy and Efficiency

High-Density SRAM Read Access Yield Estimation Methodology

Yield driven design and optimization for near-threshold voltage SRAM cells

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