2016
DOI: 10.1117/1.jmm.15.1.013501
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Importance of surface modification of a microcontact stamp for pattern fidelity of soluble organic semiconductors

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Cited by 9 publications
(7 citation statements)
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“…To investigate the bulk effect of the photoresponsive PVP gate insulator on the photoresponse, we fabricated two OPTs with different thicknesses (d) of the PVP gate insulator on the SiO 2 insulators; the values of d in the two different devices were approximately 60 and 260 nm (see Figure 1 for the schematic structure). It is noteworthy that the SiO 2 layers were exploited as first gate insulators such that the electrical characteristics of the OPTs were not changed significantly, even with the thinnest d of 60 nm [18,19,23,24]. As shown in Figure S2, gate leakage current levels of the two OPTs with different PVP thickness (d = 60 and 260 nm) were compared.…”
Section: Resultsmentioning
confidence: 99%
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“…To investigate the bulk effect of the photoresponsive PVP gate insulator on the photoresponse, we fabricated two OPTs with different thicknesses (d) of the PVP gate insulator on the SiO 2 insulators; the values of d in the two different devices were approximately 60 and 260 nm (see Figure 1 for the schematic structure). It is noteworthy that the SiO 2 layers were exploited as first gate insulators such that the electrical characteristics of the OPTs were not changed significantly, even with the thinnest d of 60 nm [18,19,23,24]. As shown in Figure S2, gate leakage current levels of the two OPTs with different PVP thickness (d = 60 and 260 nm) were compared.…”
Section: Resultsmentioning
confidence: 99%
“…No significant difference in gate leakage current between these two devices was observed. This may be attributed to the high-quality insulating property of the first gate insulator (SiO 2 ) [18,19,23,24]. Figure 2 shows the transfer curves of the OPTs obtained for gate voltages (V g ) from 50 to −50 V at the drain voltage (V d ) of −50 V. The mobility was approximately 0.16 cm 2 /Vs for both d = 60 and 260 nm.…”
Section: Resultsmentioning
confidence: 99%
“…A heavily doped p-type Si wafer was used as a gate electrode, and 300-nm-thick thermally grown SiO 2 on the Si substrates was used as the first gate insulator. Note that SiO 2 was used because of its high insulating property [16]. The substrate was cleaned with acetone, isopropyl alcohol, methanol, and deionized water in sequence.…”
Section: Methodsmentioning
confidence: 99%
“…On the PDMS stamp, O 2 plasma treatment (Cute plasma system, Femto Science; plasma generating frequency of 50 kHz) was followed for 40 s at the flow rate of 30 sccm for O 2 gas at 70 W under the pressure of 0.5 Torr. The top Au layer together with the CYTOP nanopillars was peeled off using the PDMS stamping method to leave only six circular unit patterns of 2 mm in diameter on the MIM sample, complementary to the patterns of the PDMS stamp. Note that this is possible because the adhesion between the CYTOP layer and the bottom Au layer is relatively weak at the interface.…”
Section: Methodsmentioning
confidence: 99%