Improve Image Decoding in Lightweight Environment Using a Coroutines Based Approach

Saoungoumi-Sourpele, Rodrigue; Nlong, Jean Michel; Kamdjoug, Jean-Robert Kala; Yufui, Glen Vernyuy

doi:10.4236/jcc.2020.810007

Cited by 3 publications

(1 citation statement)

References 16 publications

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“…Saoungoumi-Sourpele et al in [17] observed that the successor of JPG, JPEG2000 for image compression, is still slow because of the COder-DECoder (CODEC) complexity that it holds. This process involves a lot of energy resources, memory, computation time and CPU.…”

Section: Ravi Et Al Developed An Algorithm Using 2dwt-a Technique For...mentioning

confidence: 99%

Implementation of FPGA hardware architecture for optimized SPIHT coder using 2DWT-A

2022

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During multimedia communication and in Health care IOT, we transmit medical images and other information to health care experts, caretakers and relatives with faster speed. Remote monitoring gains periodical data and can be transported to the cloud due to its massive nature. This huge data can accommodate larger bandwidth and reduces the speed of operation. Hence, image compression is crucial for multimedia data communication. The proposed work develops an integrated architecture for both image transform and SPIHT based encoding process. We have selected the SPIHT algorithm for image compression because of its several expedient features. Parallel pipelined poly-phase two dimensional discrete wavelet transform based image transform architecture has been designed and implemented with reduced hardware and latency. The SPIHT encoder receives the low frequency components from the 2DWT-A image transformer. We removed other high frequency components to reduce the number of coefficients for transmission. In SPIHT encoder architecture, the hardware efficient binary arithmetic encoder with position control unit is used to avoid prefix zeros during arithmetic computation which replaces the hardware expensive arithmetic coders. This increases the speed of operation of the image codec. This brings effective hardware utilization into focus. Xilinx FPGA device with Microblaze core processor and SPARTAN 3EDK kit is used for realization of the hardware architecture. We use image codec architecture enactment principle for examination. We compare the performance of the proposed architecture with the existing schemes. The requirements, power and delay for the proposed method are optimized considerably when compared to the existing techniques. It reduces the area of the designed system while increasing the frequency by a factor of 2.1MHz. We use 180nm CMOS technology in Cadence tool for estimating the performance at cell level.

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Section: Ravi Et Al Developed An Algorithm Using 2dwt-a Technique For...mentioning

confidence: 99%

Implementation of FPGA hardware architecture for optimized SPIHT coder using 2DWT-A

2022

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Evolution of Kotlin Apps in terms of Energy Consumption: An Exploratory Study

Ahmed,

Boshchenko,

Khan

et al. 2023

2023 International Conference on ICT for Sustainability (ICT4S)

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On Analyzing Virtual Threads – a Structured Concurrency Model for Scalable Applications on the JVM

Beronic

Pufek

Mihaljević

et al. 2021

2021 44th International Convention on Information, Communication and Electronic Technology (MIPRO)

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Improve Image Decoding in Lightweight Environment Using a Coroutines Based Approach

Cited by 3 publications

References 16 publications

Implementation of FPGA hardware architecture for optimized SPIHT coder using 2DWT-A

Implementation of FPGA hardware architecture for optimized SPIHT coder using 2DWT-A

Evolution of Kotlin Apps in terms of Energy Consumption: An Exploratory Study

On Analyzing Virtual Threads – a Structured Concurrency Model for Scalable Applications on the JVM

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