Improved analog/RF performance of double gate junctionless MOSFET using both gate material engineering and drain/source extensions

Chebaki, Elasaad; Djeffal, F.; Ferhati, H.; Bentrcia, Toufik

doi:10.1016/j.spmi.2016.02.009

Cited by 45 publications

(9 citation statements)

References 24 publications

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“…Finally, to evaluate the significance of a VSTB FET, it is necessary to compare its performance to that of other non‐classical devices. In this regard, the overall performance estimated in this work is compared with the reported results of few published articles in Table 3 17,18,48–56 . It is noticed that a VSTB FET yields a comparable performance as any other modern device; however, the structural complexity is minimal in the case of this new structure.…”

Section: Resultsmentioning

confidence: 86%

Study of enhanced DC and analog/radio frequency performance of a vertical super‐thin body FET by high‐k gate dielectrics

Barman

Baishya

2021

Int J RF Microw Comput Aided Eng

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This article reports the DC and analog/radio frequency (RF) response of a newly invented device called vertical super‐thin body (VSTB) FET towards high‐k (Si3N4/HfO2) and low‐k (SiO2) gate dielectrics in conjunction with the scaling effect through a well‐calibrated Sentaurus TCAD tool. At channel length (LG) of 20 nm, compared to SiO2, Si3N4 improves various DC parameters such as off‐state leakage current (Ioff), on‐current (Ion), on‐to‐off current ratio (Ion/Ioff ratio), subthreshold swing (SS), and drain‐induced‐barrier‐lowering (DIBL) by 77.15%, 26.2%, one order of magnitude, 15.78%, and 36.2%, respectively. On the other hand, a higher improvement is seen in all these DC parameters for the HfO2 gate dielectric (Ioff, Ion, Ion/Ioff ratio, SS, DIBL improves respectively by 91.8%, 41.57%, two orders of magnitude, 28.28%, and 62.71%). The underlying physics behind such excellent improvement is explained by the device off‐state energy band diagram, electrostatic potential, and channel electron density profile for each dielectric. Further, for all the gate dielectrics considered, the device characteristics were studied for a wide range of LG from 10 to 50 nm to reveal the scaling impact on the device performance. Irrespective of the gate dielectric material, the device exhibits excellent performance at LG = 10 nm, which in turn indicates to the brilliant scalability of this new device. Besides, although Si3N4 and HfO2 increase gate capacitance (Cgg)/gate‐drain capacitance (Cgd), due to the extremely low values of Cgg/Cgd, enhanced unit gain cut‐off frequency, and gain‐bandwidth‐product is achieved. In addition, the increased transconductance (gm) of the device applying Si3N4/HfO2 gate dielectric leads to a higher peak value of TGF, intrinsic gain, TFP, GFP, and GTFP. This study intends to expand the fundamental knowledge about such a new device as a VSTB FET and hence, aims to be utilized in the future research of this novel device.

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Section: Resultsmentioning

confidence: 86%

Study of enhanced DC and analog/radio frequency performance of a vertical super‐thin body FET by high‐k gate dielectrics

Barman

Baishya

2021

Int J RF Microw Comput Aided Eng

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“…From the plot, it is evident that increasing intrinsic gain is obtained for increasing t ch . 26 Due to R o dominance over g m , a higher value of gain is achieved for increased t ch values.…”

Section: Geometrical Parameter Variationsmentioning

confidence: 99%

Investigation of geometrical and doping parameter variations on GaSb/Si‐based double gate tunnel FETs: A qualitative and quantitative approach for RF performance enhancement

Shanmuganathan

Balasubramanian

2019

Int J Numerical Modelling

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This paper compares the radio frequency (RF) performance enhancement of GaSb/Si‐based double gate (DG) tunnel field‐effect transistors (TFETs) and DG TFETs with gate‐drain overlap devices using technology computer‐aided design (TCAD) simulations. The geometrical parameters taken under consideration are gate length (Lg), gate oxide thickness (tox), channel thickness (tch), and doping parameters are channel doping (Nch), drain doping (Nd), and source doping (Ns). These parameters are varied to extract the RF parameters, cut‐off frequency (ft), maximum oscillation frequency (fmax), intrinsic gain, and admittance (Y) parameters. DG TFET with gate‐drain overlap offers highest fmax values of 977 GHz for drain doping of 1e20 cm−3. Higher values of output resistance (Ro) results in high intrinsic gain values for DG TFET with gate‐drain overlap. In terms of Y parameters, DG TFET with gate‐drain overlap shows better Y11 and Y22 values compared with DG TFET. A quantitative model as a function of geometrical and doping parameters is modelled for all the RF parameters that validate the simulated values and predicted values.

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“…The complementary metal-oxide-semiconductor (CMOS) technology has advanced through the decades to dominate the semiconductor industry with excellent features of low power and cost, dense packaging, and high-speed devices that are continuously scaled down in size [1][2][3]. When it comes to designing RF/analog circuits in the nanometer regime, several challenges have been encountered due to strict process requirements to maintain sharp source/drain region and short channel effects (SCEs) [4][5][6][7]. The junctionless eld-effect transistor (JLFET) solves many of the issues related to SCEs but still, it suffers from poor carrier mobility due to high channel doping, which leads to transconductance/gain degradation and hence low ON current [8,9].…”

Section: Introductionmentioning

confidence: 99%

Design and Parametric Variation Assessment of Dopingless Nanotube Field-Effect Transistor (DL-NT-FET) for High Performance

Singh

Chakraborty

Kumar

2021

Silicon

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In this paper, a dopingless nanotube eld-effect transistor (DL-NT-FET) has been proposed and its performance analysis is done using a technology computer-aided design (TCAD) tool, ATLAS provided by Silvaco. The elimination of doping is brought in by the application of the charge-plasma (CP) technique.A comparative examination of transfer characteristics (I D -V GS ), transconductance (g m ), gate capacitances (C gs and C gd ), output characteristics (I D -V DS ), output conductance (g ds ), average subthreshold slope (AVSS), the threshold voltage (V t ), the ratio of on-current to off-current (I ON /I OFF ) and on-current has been made by varying the channel length (Lg), radius (R), gate work function (Φ), and temperature. Results revealed that increasing the channel length improves subthreshold slope with greater I ON /I OFF and less threshold voltage. It has been also noticed that increase in the radius of the nanotube or an increase in temperature results in just the opposite effect of that observed in the case of increasing channel length. The I OFF value increases signi cantly on increasing the temperature while the small degradation in the I ON has been noticed as a result of mobility degradation and velocity saturation. The I ON degrades 15% by increasing the temperature from 200K to 400K. The output conductance g ds also degrades on increasing the temperature. A proliferation of 39% is observed in the C gs at the V GS of 0.45V on increasing the channel length from 20 nm to 35 m whereas no signi cant changes are observed in the C gd for the same increment in the channel length.

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Improved analog/RF performance of double gate junctionless MOSFET using both gate material engineering and drain/source extensions

Cited by 45 publications

References 24 publications

Study of enhanced DC and analog/radio frequency performance of a vertical super‐thin body FET by high‐k gate dielectrics

Study of enhanced DC and analog/radio frequency performance of a vertical super‐thin body FET by high‐k gate dielectrics

Investigation of geometrical and doping parameter variations on GaSb/Si‐based double gate tunnel FETs: A qualitative and quantitative approach for RF performance enhancement

Design and Parametric Variation Assessment of Dopingless Nanotube Field-Effect Transistor (DL-NT-FET) for High Performance

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