Improved Assertion Lifetime via Assertion-Based Testing Methodology

Riazati, Mohammad; Mohammadi, Siamak; Afzali-Kusha, Ali; Navabi, Z.

doi:10.1109/icm.2006.373264

Cited by 3 publications

(3 citation statements)

References 12 publications

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“…However in case of non-scan circuits its main bottleneck is observability. A method for verification assertions synthesis to hardware assertion checkers embedded to the circuits for on-line testing is proposed by Riazati, Navabi et al in [6], [7] and by Boule in [9]. The other approaches meant for prototype validation mentioned in the first section can be extended for this purpose.…”

Section: Assertion-based Bistmentioning

confidence: 99%

“…Please see There have been proposed methods in our previous works [3], [4] for test generation based on design properties, however the properties themselves were not automatically obtained. The methods considering assertions reusability for testing were also recently proposed by Riazati, Navabi et al in [6], [7] and Boule and Zilic in [8], [9] however they have several limitations and focused only on test pattern generation by the synthesized checkers. The approaches do not consider other aspects of test plan development and lead to large area overhead.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

On reusability of verification assertions for testing

Jenihhin

Raik

Ubar

et al. 2008

2008 11th International Biennial Baltic Electronics Conference

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Assertions have proven to be an effective mechanism to improve quality and to speed-up simulationbased design verification. They are created and embedded to the simulatable design description by the designer, the person with the deepest knowledge about the desired functionality and its real implementation. In this paper we propose to reuse this valuable information during the design manufacturing testing phase to increase the test quality and efficiency. The paper considers different types of design properties created for verification such as environmental assumptions and internal signal assertions. The reusable information is proposed to be applied for test pattern generation, embedded test observability improvement and DfT (design for testability) enhancement.

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Section: Assertion-based Bistmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

On reusability of verification assertions for testing

Jenihhin

Raik

Ubar

et al. 2008

2008 11th International Biennial Baltic Electronics Conference

View full text Add to dashboard Cite

show abstract

“…It proposed the use of assertions only at the critical points in the design to create a minimal overhead and speed reduction. Riazati et al have synthesized assertions for a basic CPU design for detection of stuck-at faults and presented the overhead resources needed for their implementation [13]. The effectiveness of an assertion checker is measured through a performance metric that is proportional to the area overhead and fault coverage of the corresponding checker.…”

Section: Assertion-based Verificationmentioning

confidence: 99%

Performance and area optimization for reliable FPGA-based shifter design

Syed¹

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Performance and Area Optimization for Reliable FPGA-based Shifter Design by Zahid Ali Syed Master of Science in Electrical Engineering West Virginia University Afzel Noore, Ph.D., ChairThis thesis addresses the problem of implementing reliable FPGA-based shifters. An FPGA-based design requires optimization between performance and resource utilization, and an effective verification methodology to validate design behavior. The FPGA-based implementation of a large shifter design is restricted by an I/O resource bottleneck. The verification of the design behavior presents a further challenge due to the 'black-box' nature of FPGAs. To tackle these design challenges, we propose a novel approach to implement FPGA-based shifters. The proposed design alleviates the I/O bottleneck while significantly reducing the logic resources required. This is achieved with a minimal increase in the design delay. The design is seamlessly scalable to a multi-FPGA chip setup to improve performance or to implement larger shifters. It is configured using assertion checkers for efficient design verification. The assertion-based design is further optimized to alleviate the performance degradation caused by the assertion checkers.iii

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Assertion based on-line fault detection applied on UHF RFID tag

Mezzah

Kermia

Chemali

et al. 2013

2013 8th IEEE Design and Test Symposium

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International audienceIn this paper, we propose a new RFID tag monitoring approach, based on adding an infrastructure circuit to simultaneously monitor and save faulty tag behaviour, in order to enable the implementation of advanced RFID diagnosis functions and mainly to reinforce tag security against fault attacks. The added infrastructure circuit is essentially composed of hardware assertions exclusively devoted to on-line fault detection on the tag. Saved information about detected faults can then be read using RFID readers. Our approach is initially evaluated and implemented in a developed tag emulator platform based on an FPGA board, then thoroughly exercised to demonstrate its valuable contribution to diagnosis means. Experimental results, obtained via random fault injection mechanism, show the effectiveness of the proposed approach

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Improved Assertion Lifetime via Assertion-Based Testing Methodology

Cited by 3 publications

References 12 publications

On reusability of verification assertions for testing

On reusability of verification assertions for testing

Performance and area optimization for reliable FPGA-based shifter design

Assertion based on-line fault detection applied on UHF RFID tag

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