Improved characteristics of charge-trapping flash device with tunneling layer formed by low temperature nitrogen-rich SiN/SiO<inf>2</inf> stack

Abstract

For better performance on charge-trapping(CT) flash device, tunneling layer stacks of nitrogen(N)-rich SiN/SiO 2 and low temperature(LT) N-rich SiN/SiO 2 are studied. The programming and erasing speeds of CT flash device are significantly improved by the tunneling layer stacks due to the lower conduction and valence band offsets of N-rich and LT N-rich SiN. The retention properties of CT flash devices with standard SiN trapping layer are satisfactory. Introduction: Recently, nitride-based flash device has attracted great interest for nonvolatile memory applications. It is widely applied to portable electronic products such as smart phone and laptop PC. For the need of higher device density, some 3D device structures have been proposed [1], and they are all based on silicon nitride (SiN) trapping layer. CT flash devices are greatly influenced by the process parameters of SiN layer. However, only Si-rich SiN used as trapping layer is commonly reported. With smaller bandgap, the erasing speed of Si-rich SiN trapping layer device is faster than that of standard SiN trapping layer device. The erasing speed of N-rich SiN trapping layer device is not fast as well because N-rich SiN has shallower hole trap. Furthermore, it is known that SiN deposited at lower temperature(600°C) has lower bandgap and shallower trap level [2]. But the effects of N-rich SiN and low temperature N-rich SiN (LT N-rich SiN) for tunneling oxide stack are rarely reported. In this work, the tunneling layer stacks of Nrich SiN/SiO 2 and LT N-rich SiN/SiO 2 on CT flash device are studied. Different trapping layer (standard SiN and Si-rich SiN) are compared as well. Experimental: Flash capacitors were fabricated on p-type Si (100) wafer. Samples with two different trapping layers, standard SiN and Si-rich SiN, divide all the samples into two parts. In each part, the effects of tunneling layers composed of simply SiO 2 , N-rich SiN/SiO 2 , and LT Nrich SiN/SiO 2 are compared. The fabrication process and structure graph are shown in Fig. 1. Note that SiO 2 and SiN were all formed by RTO and LPCVD, respectively. Split table and detailed LPCVD SiN process parameter are listed in Table 1 and Table 2, respectively. Results and Discussion: The programming and erasing (P/E) speeds of samples with standard SiN trapping layer are shown in Fig. 2 and Fig. 3, respectively. It can be seen that the P/E speeds of stacked tunneling layer samples are faster than that of single tunneling layer one. This is because the conduction and valence band offsets of N-rich and LT N-rich SiN are smaller than that of SiO 2 , resulting in a shorter tunneling length of the stacked layer seen by carriers [3]. The P/E speeds of LT N-rich SiN/SiO 2 stacked sample are faster than that of N-rich SiN/SiO 2 stacked one. This is because the bandgap for low temperature deposited SiN is smaller. The retention performance of stacked tunneling layer samples becomes a little worse as shown in Fig. 4 while higher erasing speed is achieved. This is because electrons in trapping layer are easier t...