Improved cryptanalysis of step-reduced SM3

Shen, Yanzhao; Bai, Dongxia; Yu, Haiyan

doi:10.1007/s11432-017-9119-6

Cited by 1 publication

(3 citation statements)

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“…This solution is implemented in software and its throughput is not reported. In the work of [23], two different attacks on SM3 are introduced. The authors mainly studied the improvement of the resistance to attacks, but the internal details of the architecture were not reported, and thus we only discuss and compare the related implementation approaches.…”

Section: Comparison With Other Related Workmentioning

confidence: 99%

“…In [25], authors combine the implementation with the ARM processor to enhance the throughput. Because of lack of detailed data in [21][22][23], no direct comparison can be made with the work.…”

Section: Comparison With Other Related Workmentioning

confidence: 99%

“…For instance, in article [13], authors adopt the software/hardware co-design method to implement SM3, which is applied to the financial IC card. Moreover, the different optimized SM3 architecture and methods, such as the 3-stage pipeline approach, the parallel implementation strategy, the optimized architecture adopted the CSA adder, the implementation with the embedded ARM core, etc., are proposed [20][21][22][23][24][25]. Previous work promotes the development of SM3 VLSI architecture which has the characteristics of small hardware area and low power consumption.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An Efficient and Low-Power Design of the SM3 Hash Algorithm for IoT

Zheng

Zhang

et al. 2019

Electronics

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The Internet-of-Things (IoT) has a security problem that has become increasingly significant. New architecture of SM3 which can be implemented in loT devices is proposed in this paper. The software/hardware co-design approach is put forward to implement the new architecture to achieve high performance and low costs. To facilitate software/hardware co-design, an AHB-SM3 interface controller (AHB-SIC) is designed as an AHB slave interface IP to exchange data with the embedded CPU. Task scheduling and hardware resource optimization techniques are adopted in the design of expansion modules. The task scheduling and critical path optimization techniques are utilized in the compression module design. The proposed architecture is implemented with ASIC using SMIC 130 nm technology. For the purpose of comparison, the proposed architecture is also implemented on Virtex 7 FPGA with a 36 MHz system clock. Compared with the standard implementation of SM3, the proposed architecture saves the number of registers for approximately 3.11 times, and 263 Mbps throughput is achieved under the 36 MHz clock. This design signifies an excellent trade-off between performance and the hardware area. Thus, the design accommodates the resource-limited IoT security devices very well. The proposed architecture is applied to an intelligent security gateway device.

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Section: Comparison With Other Related Workmentioning

confidence: 99%

Section: Comparison With Other Related Workmentioning

confidence: 99%