Improved DC Performance Analysis of a Novel Asymmetric Extended Source Tunnel FET for Fast Switching Application

Abstract

A two-dimensional analytical model for asymmetric extended source tunnel field effect transistor (AES-TFET) has been developed to obtain better device performance. The proposed device model has been analytically modelled and performed by solving 2-D Poisson’s equation. Surface potential distribution, electric field variation and band-to-band tunneling (BTBT) rate have been investigated by this numerical modelling. The source region of novel structure of TFET has been extended (varied 2 nm to 6 nm) to incorporate corner effect, which allows BTBT through a thin tunneling barrier, with controlled ambipolar conduction. This eventually produces better source-channel interface tunneling for a n-channel AES-TFET. 2-D numerical device simulator (SILVACO TCAD) has been used for simulation work. The simulated work has been finally validated by analytical modelling of AES-TFET. Better ION, IOFF and switching ratio has been obtained from this novel TFET structure.

Tunnelling FETs, the Non-conventional Transistors: Basics

“…Both these things make this device a prime candidate in low-power circuits. The tunnelling FET, as lies in the name itself, modulates the quantum tunnelling through the barrier rather than the thermionic emission over the barrier for the conventional transistor [11]. This phenomenon will be further discussed in the following sections.…”