Improved Design and Comparison of a Low Power CNTFET based on D Flip-Flop

Ridoy, Jahid Hasan; Rahman, Atik Yasir; Saquib, Fahad Raihan

doi:10.1109/ecce57851.2023.10101615

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2024

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“…This article, [5], introduces the predictable parameter of CNTFET. Where leakage current and power of the proposed D flip-flop had a better design compared with various other circuits.…”

Section: Introductionmentioning

confidence: 99%

Design of Low Power Ternary Logic Encoder and ADC using CNTFET

M. B.,

2024

Wseas Transactions on Electronics

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Ternary logic has received substantial attention over the past decade due to its compensations of smaller chip area and interconnection compared to outmoded binary logic. Carbon Nanotube Field Effect Transistor (CNTFET) technology is widely used for ternary logic implementation due to its versatile threshold voltages. The increased power consumption in current designs utilizing CNFETs, as linked to binary logic, is attributed to elevated static power dissipation within the design. This work recommends alternative triple encoder designs with a focus on reducing the consumption of power. The model uses an additional Vdd/2 supply voltage to decrease static power dissipation and encoder power delay. Cadence virtuoso-based circuit simulations are implemented for the proposed encoder design.

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“…This article, [5], introduces the predictable parameter of CNTFET. Where leakage current and power of the proposed D flip-flop had a better design compared with various other circuits.…”

Section: Introductionmentioning

confidence: 99%

Design of Low Power Ternary Logic Encoder and ADC using CNTFET

M. B.,

2024

Wseas Transactions on Electronics

View full text Add to dashboard Cite

show abstract

Improved Design and Comparison of a Low Power CNTFET based on D Flip-Flop

Cited by 1 publication

References 11 publications

Design of Low Power Ternary Logic Encoder and ADC using CNTFET

Design of Low Power Ternary Logic Encoder and ADC using CNTFET

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