Improved design of high‐frequency sequential decimal multipliers

Abstract

Hardware implementation of decimal arithmetic operations has become a hot topic for research during the last decade. Among various operations, decimal multiplication is considered as one of the most complicated dyadic operations, which requires high-cost hardware implementation. Therefore, the processor industry has opted to use the sequential decimal multipliers to reduce the high cost of parallel architectures. However, the main drawback of iterative multipliers is their high latency. In this reported work, the focus has been on reducing the latency of decimal sequential multipliers while maintaining a low cost of area. Consequently, a high-frequency sequential decimal multiplier is proposed whose cycle time is reduced to the latency of a binary half-adder plus that of a decimal multiply-by-two operation, which overall is less than that of a decimal carry-save adder. The synthesis results reveal that the proposed sequential multiplier works with a higher clock frequency than the fastest previous decimal multiplier which in turn leads to overall latency advantage.Introduction: Hardware implementation of decimal floating-point arithmetic has been gaining revived popularity during the last decade. However, the complexity of the decimal number system brings about more challenges to be dealt with during the hardware implementation, compared with the binary counterparts. With the intention to reduce the high cost of these decimal operations the processor industry has opted for sequential realisation [1]. However, sequential hardware realisation is at a disadvantage because of its high latency.This Letter focuses on the hardware realisation of the decimal multiplication and a novel architecture is proposed to ameliorate the problem of slow sequential decimal multipliers via increasing the clock frequency. In this design, the cycle time is reduced to the latency of a binary half-adder (HA) plus that of a decimal multiply-by-two operation, which overall is less than that of a decimal carry-save adder (CSA). The claimed improvement is supported by synthesising and comparing the proposed design to those of the best previous pertinent works.The proposed design includes the following novelties, with respect to previous works:

Efficient Realization of BCD Multipliers Using FPGAs

“…In [9], Radix5 recoding was combined with BCD code converters using BCD4221 and BCD5211 codes to simplify the partial product generation and reduction. In the recent two years, some ASIC-based designs for the realization of decimal multiplication were proposed in [10][11][12][13][14]. The recoding methods and BCD code conversions were used in these designs for efficient implementation in ASIC.…”