Microelectronic Engineering
 2006
DOI: 10.1016/j.mee.2006.10.040
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Improved electrical and reliability performance of 65nm interconnects with new barrier integration schemes

R. Delsol1,
J.P. Jacquemin2,
M. Gregoire
3
et al.
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Cited by 4 publications
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Post electrochemical Cu deposition anneal impact on stress-voiding in individual vias

Gregoire
1
,
Juhel
2
,
Vannier
3
et al. 2008
Microelectronic Engineering
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Post electrochemical Cu deposition anneal impact on stress-voiding in individual vias

Gregoire
1
,
Juhel
2
,
Vannier
3
et al. 2008
Microelectronic Engineering
4
2
1
0
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Effect of sputtering bias voltage on the structure and properties of Zr–Ge–N diffusion barrier films

Lin
1
,
Liu
2
,
Ren
3
et al. 2013
Surface and Coatings Technology
10
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0
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Interconnects for nanoscale MOSFET technology: a review

Chaudhry1
2013
J. Semicond.
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