Improved electrical properties of micro light-emitting diode displays by ion implantation technology

Abstract

Generally, the inductively coupled plasma-reactive ion etching (ICP-RIE) mesa technology was used to remove p-GaN/MQWs and expose n-GaN for electrical contact in a fabricated micro light-emitting diode (μLED). In this process, the exposed sidewalls were significantly damaged which result in small-sized μLED presenting a strong size-dependent influence. Lower emission intensity was observed in the μLED chip, which can be attributed to the effect of sidewall defect during etch processing. To reduce the non-radiative recombination, the ion implantation using an As+ source to substitute the ICP-RIE mesa process was introduced in this study. The ion implantation technology was used to isolate each chip to achieve the mesa process in the μLED fabrication. Finally, the As+ implant energy was optimized at 40 keV, which exhibited excellent current–voltage characteristics, including low forward voltage (3.2 V @1 mA) and low leakage current (10–9 A@− 5 V) of InGaN blue μLEDs. The gradual multi-energy implantation process from 10 to 40 keV can further improve the electrical properties (3.1 V @1 mA) of μLEDs, and the leakage current was also maintained at 10–9 A@− 5 V.

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“…Moreover, ion implantation with an As þ source has been used to replace the plasma-etching mesa process in the fabrication of GaN lLEDs. 97 The optimal As þ implantation process at 40 keV demonstrated excellent I-V characteristics, including a forward voltage of 3.1 V at 1 mA and a leakage current of 10 À9 A at À5 V for InGaNbased blue lLEDs.…”

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“…This observation was further supported by the results of SIMS. As the implantation depth increased, the forward voltage also increased from sample A, B, to C, indicating that the n-GaN layer was more severely damaged, leading to an increase in the series resistance of the device from 206 Ω to 222 Ω under a 20 mA current injection, respectively, owing to deeper ion implantation [35]. The schematic representation of series resistance, R s , and parallel resistance, R p , in the device structure is shown in Fig.…”