2006
DOI: 10.1109/tcsi.2006.880316
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Improved First-Order Time-Delay Tanlock Loop Architectures

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Cited by 25 publications
(23 citation statements)
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“…17,18 It is shown that the real-time performance of the TDTL compares favorably with the simulation results obtained from the MATLAB/SIMULINK model. The synthesis process of the prototype system used Xilinx System Generator to generate the necessary hardware description language (HDL) for the device-optimized block-set from within SIMULINK.…”
Section: Methodsmentioning
confidence: 77%
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“…17,18 It is shown that the real-time performance of the TDTL compares favorably with the simulation results obtained from the MATLAB/SIMULINK model. The synthesis process of the prototype system used Xilinx System Generator to generate the necessary hardware description language (HDL) for the device-optimized block-set from within SIMULINK.…”
Section: Methodsmentioning
confidence: 77%
“…In addition, the system has a controllable variable time delay module which is used in conjunction with the PV source voltage to emulate the functionality of the digital controlled oscillator (DCO) used in the conventional TDTL system. [16][17][18] A continuous sinusoidal signal yðtÞ, representing the grid voltage, as defined by Eq. (1) with a phase offset xðt À t o Þ relative to the PV voltage waveform PðtÞ is received by the proposed system, through an appropriate interface, as depicted in Figure 2.…”
Section: Analysis Of the Systemmentioning
confidence: 99%
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“…Therefore, the difference equation was solved numerically using the fixed point theorem [12][13][14] as in the case applied to the zero-crossing digital phase lock loop [12,15,16]. (13) and (14), the system difference equation of the second order TDTL can be derived as…”
Section: λ = ∆mentioning
confidence: 99%