1992
DOI: 10.1109/55.145073
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Improved InAlAs/InGaAs HEMT characteristics by inserting an InAs layer into the InGaAs channel

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Cited by 113 publications
(31 citation statements)
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“…An I C of about 5 A and an R N of 16 ⍀ were obtained at V g ϭ0 V. The I C was almost completely suppressed at V g ϳϪ0.9 V and R N was increased to 1.46 M⍀ at V g ϭϪ1. 15 V. Note that no gate-leakage current was observed at V g ϭϪ1.15 V. These results show a remarkable improvement in controllability of both I C and R N via gate voltage, compared with the JOFET that used the MIS-type gate. This is because the interface between the gate electrode and the undoped InAlAs layer is free from the interface levels, while SiO 2 was used as the gate insulator in the MIStype gate with the interface levels at the SiO 2 /InAlAs interface.…”
Section: Ntt Basic Research Laboratories 3-1 Morinosato-wakamiya Atmentioning
confidence: 67%
See 1 more Smart Citation
“…An I C of about 5 A and an R N of 16 ⍀ were obtained at V g ϭ0 V. The I C was almost completely suppressed at V g ϳϪ0.9 V and R N was increased to 1.46 M⍀ at V g ϭϪ1. 15 V. Note that no gate-leakage current was observed at V g ϭϪ1.15 V. These results show a remarkable improvement in controllability of both I C and R N via gate voltage, compared with the JOFET that used the MIS-type gate. This is because the interface between the gate electrode and the undoped InAlAs layer is free from the interface levels, while SiO 2 was used as the gate insulator in the MIStype gate with the interface levels at the SiO 2 /InAlAs interface.…”
Section: Ntt Basic Research Laboratories 3-1 Morinosato-wakamiya Atmentioning
confidence: 67%
“…The growth temperature for all layers was kept at about 300°C, since the critical thickness increases at lower growth temperatures. 14 Using the results from our previous reports, 15,16 we fixed the InAs quantum-well thickness at 4 nm and the insertion position ͑the distance between the InAlAs spacer layer and the InAs quantum well͒ at 2.5 nm. In this way, a 2DEG was confined in the inserted InAs layer.…”
Section: Ntt Basic Research Laboratories 3-1 Morinosato-wakamiya Atmentioning
confidence: 99%
“…This InGaAs/InAlAs heterostructure is lattice-matched with InP, which can be easily integrated with other devices for di erent application purposes. The inserted InAs well, under the critical thickness, can provide the higher electron mobility [6]. The g factor in this system can be expected to have contributions from all materials.…”
Section: Introductionmentioning
confidence: 98%
“…The InAlAs ternary alloy, lattice matched to InP substrates is potentially of importance owing to its usefulness for the fabrication of optoelectronic [3,4] and high-speed electronic [5,6] devices. While the AlGaAs/GaAs material system has an abrupt hetero-interface, [7,8] the growth of InAlAs on InP substrates has been reported to be difficult.…”
Section: Introductionmentioning
confidence: 99%