Improved interconnect sharing by identity operation insertion

Abstract

This paper presents an approach to reduce interconnect cost by insertion of identity operations in a CDFG. Other than previous approaches, it is based on systematic pattern analysis and automated transformation selection. The cost function controlling transformation selection is derived with statistical experiments and is optimized using practical benchmarks. The results show significantly reduced interconnect cost for most register architectures and application examples.

Minimizing Global Interconnect in DSP Systems using Bypassing

“…Later, it was also used, under the name of deflection operations and bypassing in behavioral synthesis [3,4,5] in order to heuristically address the reduction of local interconnect and the size of registers files.…”

Increasing hardware efficiency with multifunction loop accelerators

“…Generation of more efficient designs by sharing hardware across basic blocks was recently proposed [13]. Cost sensitive scheduling, used within the synthesis system to reduce hardware cost, has been studied in the context of storage and interconnect minimization in [20,11,5] and to improve resource sharing [23].…”