Improved Magnetic Sensitivity of CMOS Vertical Hall Device by Using Partial Implantation Technique

Abstract

With the continuous scaling of CMOS technology, the doping level of N-well is constantly increasing, which leads to a big decrease in magnetic sensitivity for vertical Hall devices (VHDs). Moreover, the Gaussian profile of doping concentration gives an additional decrease in N-well effective depth, which further reduces the magnetic sensitivity. In this paper, we apply partial N-well and top p+ layer implantation techniques to lower the doping level of Nwell and improve the doping profile by means of impurity lateral diffusion and compensation effects. TCAD process and device simulations have been carried out for a typical five-contact VHD in 0.13 μm CMOS technology. Simulation results show that the current-related magnetic sensitivity is greatly improved from 40 V/AT to 110 V/AT by using the partial implantation techniques. Meanwhile, the voltage-related magnetic sensitivity is also increased and not significantly decreased.