Improved on-chip self-triggered single-event transient measurement circuit design and applications

Chen, Rongmei; Chen, Wei; Guo, Xiaoqiang; Chen, Shen; Zhang, Fengqi; Liu, Zheng; Wen, Zhao; Ding, Lili; Luo, Yan-An; Guo, Hao; Wang, Yuanming; Liu, Yinong

doi:10.1016/j.microrel.2017.03.004

Cited by 10 publications

(2 citation statements)

References 15 publications

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“…Previous studies have focused on the Single-Event Upset (SEU) characteristics, total-dose ionizing responses, and simulations of FDSOI technology [15][16][17][18][19]. However, it was found that soft errors resulting from SETs in combinational logic circuits surpassed those resulting from SEUs in storage circuits, such as flip-flops and SRAM, when the combinational logic circuit operates at a high frequency [6,[20][21][22][23]. Moreover, errors induced by SETs in logic circuits cannot be eliminated by error-correcting codes (ECCs), which are usually adopted in SEU mitigation designs [6,[22][23][24][25][26].…”

Section: Introductionmentioning

confidence: 99%

Single-Event Transient Study of 28 nm UTBB-FDSOI Technology Using Pulsed Laser Mapping

Rui

Chen

et al. 2023

Electronics

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Single-event transient (SET)-induced soft errors are becoming a more significant threat to the reliability of electronic systems in space, especially for advanced technologies. The SET pulse width, which is vulnerable to SET propagation, is a critical parameter for developing SET mitigation techniques. This paper investigates the pulse-broadening effect in the process of SET propagation in logic circuits and the SET-sensitive region distribution in the layout using the pulsed-laser mapping technique in logic circuits implemented with 28 nm Ultra-Thin Body and BOX (UTBB) FDSOI technology. The experiments were carried out at the Naval Research Laboratory (NRL) to measure the SET-induced errors and map the SET-sensitive region distribution at various clock frequencies and laser energy levels. The results illustrate that the number of errors increases with the clock frequency and energy for combinational logic circuits and that the flip-flop SEU rate is less sensitive to clock frequency. The SET pulse-broadening effect was also observed using SET mapping for an OR gate chain at different laser energy levels. In addition, the simulation results revealed the mechanism of the SET pulse-broadening effect in an OR gate chain.

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Section: Introductionmentioning

confidence: 99%

Single-Event Transient Study of 28 nm UTBB-FDSOI Technology Using Pulsed Laser Mapping

Rui

Chen

et al. 2023

Electronics

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“…As process feature sizes continue to shrink, clock frequencies continue to increase, node capacitance and supply voltage decrease, the critical charge of transient pulses is reduced [3][4][5], and waveforms are more easily captured and soft errors are formed. It has been reported that SET are the main cause of soft errors in space applications [6,7], and charge sharing may even affect multiple nodes and cause single-event multiple transients (SEMT) [8][9][10]. These problems are already common in combinatorial logic circuits.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Heavy-Ion Induced Single-Event Transient in 28 nm Bulk Inverter Chain

Liang

Chi

et al. 2020

Symmetry

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The reliability of integrated circuits under advanced process nodes is facing more severe challenges. Single-event transients (SET) are an important cause of soft errors in space applications. The SET caused by heavy ions in the 28 nm bulk silicon inverter chains was studied. A test chip with good symmetry layout design was fabricated based on the 28 nm process, and the chip was struck by using 5 kinds of heavy ions with different linear energy transfer (LET) values on heavy-ion accelerator. The research results show that in advanced technology, smaller sensitive volume makes SET cross-section measured at 28 nm smaller than 65 nm by an order of magnitude, the lower critical charge required to generate SET will increase the reliability threat of low-energy ions to the circuit, and high-energy ions are more likely to cause single-event multiple transient (SEMT), which cannot be ignored in practical circuits. The transients pulse width data can be used as a reference for SET modeling in complex circuits.

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Single-event multiple transients in guard-ring hardened inverter chains of different layout designs

Wen

Chen

et al. 2018

Microelectronics Reliability

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Improved on-chip self-triggered single-event transient measurement circuit design and applications

Cited by 10 publications

References 15 publications

Single-Event Transient Study of 28 nm UTBB-FDSOI Technology Using Pulsed Laser Mapping

Single-Event Transient Study of 28 nm UTBB-FDSOI Technology Using Pulsed Laser Mapping

Investigation of Heavy-Ion Induced Single-Event Transient in 28 nm Bulk Inverter Chain

Single-event multiple transients in guard-ring hardened inverter chains of different layout designs

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