Improved Performance of Error Controlling Codes Using Pass Transistor Logic

Chennakesavulu, M.; Prasad, T. Jayachandra; Sumalatha, V.

doi:10.1007/s00034-017-0596-4

Cited by 4 publications

(3 citation statements)

References 20 publications

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“…The force values get stored and processed in the microcontroller and mapped over the PWM. The ATMEGA gives 2 8 bytes of PWM means it gives the range of PWM pulses from 0 to 255. Using the PWM values the motor driver controls the DC motor.…”

Section: Methodsmentioning

confidence: 99%

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Motor controlled system development with force-assistance using force/torque sensor for four-axis ceiling suspension system

Jiwane

Patil

Dhanvijay

2023

IJPEDS

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Multi-axis force and torque sensors are type of transducers. They can measure force and torque in three dimensions. These sensors have multiple applications in robotic systems. The majority of these type of sensors use the strain measurement in any elastic structure. There are multiple approaches for strain measurement which include resistive strain gauge, piezo-electric and capacitive technologies. The evaluation of such a system can be done on various parameters, maximizing the acceptable sensing range while minimizing measurement errors/crosstalk is the main design challenge. In future, because force and torque sensors are necessary for service machines to interact with people in different situations, they will be widely deployed. However, it is challenging to find an appropriate force/torque sensor, and the cost is very high, because of certain design concerns and needs. This paper discusses an application based on the multi-axis force/torque sensor. A force-assisted control system has been proposed with simultaneous motorized action using force as feedback. The sensor needs and machine performance are reviewed after a thorough analysis of relevant data. This thorough investigation will benefit in the interfacing of specialized force/torque sensors to reduce crosstalk and aid in broadening the scope of service machines in which they can be used.

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Section: Methodsmentioning

confidence: 99%

“…Any reading change could be seen as false due to crosstalk. In order to attain the best accuracy in force sensing, crosstalk reduction becomes crucial [7], [8]. The gain of the amplifiers determines how well the signal conditioning and amplifier circuits function overall.…”

Section: Introductionmentioning

confidence: 99%

Motor controlled system development with force-assistance using force/torque sensor for four-axis ceiling suspension system

Jiwane

Patil

Dhanvijay

2023

IJPEDS

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“…M. Chennakesavulu, T.J. Prasad, and V. Sumalatha [17] has proposed the Error Controlling Codes Using Pass Transistor Logic. The overhead power, delay and area of FEC codes: hamming code and dual rail code, and error detecting codes: checksum and two-dimensional parity with duplication.…”

Section: Related Workmentioning

confidence: 99%

ASIC Implementation of Low Power Efficient Crosstalk Analytical by LUT-BED-CLA

Obulesu¹,

Rao²

2018

IJIES

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Nowadays, crosstalk noise is one of the major problems in VLSI design circuits. While transmitting the input information, the noise occurs in the channel. After receiving the information, the input data affect by the crosstalk. In this paper, Look Up table with Bus Encoding Decoding Carry Look Ahead adder (LUT-BED-CLA) is introduced to eliminate the crosstalk noise in the receiver side. Encoder block consists of transition detector, Type-A detector, Type-B detector, XOR stack, and Latch. Encoder output is given to the crosstalk model circuit, which is implemented in Cadence virtuoso. This crosstalk model output connects to decoder input. Decoder block contains an XOR circuit to retrieve the original data, which is given to the input of the encoder. From the encoder and decoder, the area, power, and delay was evaluated. Instead of using normal adder, CLA adder was used in counter which gave better performance. Form the crosstalk analysis, cross talk output was given to the decoder input. Even though, decoder output gave same output which was given to the encoder input. This entire work implemented in Verilog to evaluate ASIC performance for 180nm and 45nm technology. In ASIC 180nm technology, 26.3% of area, 39.67% of power, 55.53% of APP, and 26.3% of ADP is minimized in LUT-BED-CLA as well as 45nm technology, 34.4% of area, 24.1% of power, 38.62% of delay, 50.11% of APP, and 59.6% of ADP reduced in LUT-BED-CLA method compared to existing method.

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