Improved performance of nanoscale junctionless transistor based on gate engineering approach

Wang, Ying; Shan, Chan; Dou, Zheng; Wang, Liguo; Cao, Fei

doi:10.1016/j.microrel.2014.11.009

Cited by 28 publications

(10 citation statements)

References 35 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The studies show that this type of transistor has many advantages such as a lower drain leakage current, high switching speed, better I ON /I OFF current ratio, better frequency response, thermal budgets after gate formation, better subthreshold slope (SS), immunity to short-channel effects, and a simpler fabrication process compared to conventional transistors. Taking into account the goal of the transistor miniaturization process as well as the simple fabrication process of junctionless transistors, these transistors are expected to improve in performance as they are miniaturized further 17,18 . The performance of junctionless transistors is determined by its ability to conduct of current within the volume, whereas in conventional field effect transistors, the main current flows along the channel surface and below the gate oxide 19 .…”

Section: Introductionmentioning

confidence: 99%

Reducing the Drain Leakage Current in a Double-Gate Junctionless MOSFET Using the Electron Screening Effect

Bavir

Abbasi

Orouji

2021

Journal of Elec Materi

View full text Add to dashboard Cite

This study investigated the position of electrons and holes in the ON and OFF states of double-gate junctionless transistors, and then three structures were proposed to create an electron-filled region exposing the drain-side inside the channel to the electron screening effect. Formation of an electron cloud in the channel and on the drain-side damps the electric field resulting from the drain voltage as the electric field passes through the electron cloud before reaching the main channel. Accordingly, in the structure with a drain-side gate, with the electric field decay introduced by the drain to the main channel, the carrier density increased compared to other structures, eventually reducing drain leakage current and improving the channel length modulation (CLM), threshold voltage, drain induced barrier lowering effect, and subthreshold slope in this structure. In the N + pocket structure, despite the decrease in the electric field resulting from the drain voltage, the drain leakage current and the CLM were increased. In the N + SiGe pocket structure, although the electric field resulting from the drain voltage along the channel length was reduced compared to the main structure, the drain leakage current and CLM experienced an increase. Moreover, the results showed that at low drain voltages, the drain leakage current in the N + pocket structure was higher than that of the N + SiGe pocket, but at high drain voltages, the order was reversed.

show abstract

Section: Introductionmentioning

confidence: 99%

Reducing the Drain Leakage Current in a Double-Gate Junctionless MOSFET Using the Electron Screening Effect

Bavir

Abbasi

Orouji

2021

Journal of Elec Materi

View full text Add to dashboard Cite

show abstract

“…Even though this structure has many advantages the leakage current in the sub-threshold regime of Double Gate Junctionless Field Effect Transistors (DG JLFET) is considerably high. It flows through the center of the channel i.e., volume conduction occurs due to the low concentration of the depletion charge carriers [10] [11]. The necessity for materials with high work function (~5.6 eV) arises from turning the device properly OFF and lowering the subthreshold leakage current [12], which is technologically challenging.…”

Section: Introductionmentioning

confidence: 99%

An Approach For Drain Current Modeling Including Quantum Mechanical Effects For A DMDG Junctionless Field Effect Nanowire Transistor

Bora

2021

Preprint

View full text Add to dashboard Cite

This paper presents the effects of quantum confinements on the surface potential, threshold voltage, drain current, transconductance, and drain conductance of a Dual Material Double Gate Junctionless Field Effect Nanowire Transistor (DMDG-JLFENT). The carrier energy quantization on the threshold voltage of a DMDG-JLFENT is modeled, and subsequently, other parameters like drain current were analytically presented. The QME considered here is obtained under the quantum confinement condition for an ultra-thin channel, i.e., below 10 nm of Si thickness. The threshold voltage shift due to QME can be used as a quantum correction term for compact modeling of junctionless transistors. The analytical model proposed for surface potential, threshold voltage, drain current, transconductance, and drain conductance were verified by TCAD 3-D quantum simulation results which makes it suitable for SPICE compact modeling.

show abstract

“…Fabrication process of highly sharp p-n junctions at source/drain with channel in inversion-mode transistor has become a huge challenge owing to the laws of diffusion and the statistical nature of the distribution of the doping atoms in the semiconductor [5,6]. To deal with aforementioned fabrication issues, junctionless transistors (JLT) were proposed, fabricated and investigated [5][6][7][8][9]. JLT has shown a lower susceptibility to the short channel effects (SCEs).…”

Section: Introductionmentioning

confidence: 99%

Hetro-Dielectric (HD) Oxide-Engineered Junctionless Double Gate all around (DGAA) Nanotube Field Effect Transistor (FET)

Kumar

2020

Silicon

View full text Add to dashboard Cite

This paper proposed Hetero-Dielectric (HD) Oxide-Engineered Junctionless double gate all around nanotube (DGAA-NT) FET for performance enhancement in low power circuits. In HD configuration, hafnium based high-k dielectric (HfO 2 and Hf x Ti 1-x O 2 ) as gate oxide (for inner as well as outer gate oxide) is introduced on source side and SiO 2 on drain side of HD JL-DGAA-NT FET. The tunnelling width and source-to-channel barrier height are significantly increased in the HD-JL-DGAA-NT FET as compared JL-DGAA-NT FET, causes the reduction in leakage current an order of 10 −14 to 10 −17 and I ON /I OFF ratio increased by 54%. It has been observed that side spacer with suitable dielectric constant can be considered to improve the performance of device. Further, Subthreshold slope (SS) and DIBL and I ON /I OFF current ratio has shown tremendous improvement on reducing channel thickness from 10 nm to 8 nm. It has been found that in HD-JL-DGAA-NT FET provides 25% and 57% improvement in SS and DIBL respectively. Therefore, HD-JL-DGAA-NT FET with adequate design parameters and dielectric material may be used for future digital applications.

show abstract

Improved performance of nanoscale junctionless transistor based on gate engineering approach

Cited by 28 publications

References 35 publications

Reducing the Drain Leakage Current in a Double-Gate Junctionless MOSFET Using the Electron Screening Effect

Reducing the Drain Leakage Current in a Double-Gate Junctionless MOSFET Using the Electron Screening Effect

An Approach For Drain Current Modeling Including Quantum Mechanical Effects For A DMDG Junctionless Field Effect Nanowire Transistor

Hetro-Dielectric (HD) Oxide-Engineered Junctionless Double Gate all around (DGAA) Nanotube Field Effect Transistor (FET)

Contact Info

Product

Resources

About