Improved Serial Peripheral Interface Controller Based on Scan Architecture

Abstract

A high performance, digital serial controller having a self-test-based architecture is presented. A standard architecture able to achieve the targeted functionality was modified in order to contain the test mode circuitry for testability improvements. After the importance of creating digital architectures adapted for testability is underlined, we present the high frequency serial controller for analog switches. This block was adjusted for test reasons and implemented into a 3 V CMOS technology. The block is integrated together with input-output pad structures forming an entire chip structure for which the layout was implemented. Based on schematic design simulations, timing checks and defects analysis, the proposed architecture is confirmed.