Improved SOI LDMOS performance by using a partial stepped polysilicon layer as the buried layer

Guo, Jingwei; Hu, Shengdong; Huang, Ye; Yuan, Qi; Yang, Dong; Yang, Ling; You, Liang; Yu, Jianyi

doi:10.1016/j.mssp.2018.09.028

Cited by 9 publications

(5 citation statements)

References 23 publications

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“…The HK is filled into the trench by CVD, then etching HK and depositing SiO 2 . Next, depositing polysilicon to form a field plate (FP) [22]. (f) Etching SiO 2 trench and depositing polysilicon to form another FP.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

A novel double-gate trench SOI LDMOS with double-dielectric material by TCAD simulation study

Guo,

Dai,

Wang

et al. 2024

Semicond. Sci. Technol.

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In this paper, a novel double-gate trench silicon-on-insulator (SOI) lateral double-diffused metal oxide semiconductor field-effect transistor (LDMOS) with double-dielectric material (DGDK-LDMOS) is proposed. DGDK-LDMOS has two dielectric materials: a reverse-L-shaped high-k (HK) thin film and an low-k (LK) buried oxide layer. The HK thin film optimizes the electric field distribution on the drift region surface, attracting electric flux, and the excellent withstand voltage of the LK buried oxide layer can significantly improve the breakdown voltage (BV) and reduce specific on-resistance (Ron,sp) of the device. The modulation mechanism of LDMOS by HK thin film and LK buried oxide layer is analyzed. The results show that compared with conventional LDMOS (C-LDMOS), when the permittivity of HK thin film is 25 and the permittivity of LK buried oxide is 3, the BV of DGDK-LDMOS is increased by 89.6%, the Ron,sp is decreased by 26.4%, and the figure of merit (FOM, FOM = BV2/Ron,sp) is increased by 397.2% from 3.6 MW·cm−2 to 17.9 MW·cm−2. Meanwhile, the output characteristics, transfer characteristics, lattice temperature, AC characteristics and switching characteristics of DGDK-LDMOS are also discussed and compared.

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Section: Simulation Results and Discussionmentioning

confidence: 99%

A novel double-gate trench SOI LDMOS with double-dielectric material by TCAD simulation study

Guo,

Dai,

Wang

et al. 2024

Semicond. Sci. Technol.

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“…Scholars have obtained many results after long-term research on StBV. Some of these results have been obtained using an analytical model of StBV [8][9][10][11][12][13][14], and others are related to new structures [15][16][17][18][19][20][21][22][23][24][25][26][27], in some of which StBV can reach more than 1000 V [25][26][27]. However, when a device is turned off rapidly, there is insufficient time for an electron inversion layer to form under the BOX, which can induce a DD effect in the Micromachines 2023, 14, 887 2 of 14 substrate.…”

Section: Introductionmentioning

confidence: 99%

Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer

et al. 2023

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In this paper, the transient breakdown voltage (TrBV) of a silicon-on-insulator (SOI) laterally diffused metal-oxide-semiconductor (LDMOS) device was increased by introducing a step P-type doping buried layer (SPBL) below the buried oxide (BOX). Device simulation software MEDICI 0.13.2 was used to investigate the electrical characteristics of the new devices. When the device was turned off, the SPBL could enhance the reduced surface field (RESURF) effect and modulate the lateral electric field in the drift region to ensure that the surface electric field was evenly distributed, thus increasing the lateral breakdown voltage (BVlat). The enhancement of the RESURF effect while maintaining a high doping concentration in the drift region (Nd) in the SPBL SOI LDMOS resulted in a reduction in the substrate doping concentration (Psub) and an expansion of the substrate depletion layer. Therefore, the SPBL both improved the vertical breakdown voltage (BVver) and suppressed an increase in the specific on-resistance (Ron,sp). The results of simulations showed a 14.46% higher TrBV and a 46.25% lower Ron,sp for the SPBL SOI LDMOS compared to those of the SOI LDMOS. As the SPBL optimized the vertical electric field at the drain, the turn-off non-breakdown time (Tnonbv) of the SPBL SOI LDMOS was 65.64% longer than that of the SOI LDMOS. The SPBL SOI LDMOS also demonstrated that TrBV was 10% higher, Ron,sp was 37.74% lower, and Tnonbv was 10% longer than those of the double RESURF SOI LDMOS.

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“…Using two metal layers of aluminum material in the oxide below the drift zone gives a more uniform electric field than the normal structure and increases the breakdown voltage 1 . A stepped polysilicon layer is replaced by the buried oxide layer at the source‐side, leading to the optimized surface electric field and a higher breakdown voltage 6 . Three dielectrics are used in this arrangement, a dielectric between the source and gate zones, a dielectric between the drain and drift zones, and another one under the gate and drift zones affecting the breakdown voltage by adding a new peak in the electric field profile 13 .…”

Section: Introductionmentioning

confidence: 99%

“…Due to the advantages of silicon technology, including low current leakage, high speed, high gain, and low power losses, the LDD-SOI structure is used as one of the high-efficiency structures in high-voltage applications. [6][7][8] LDD-SOI is designed to achieve high breakdown voltage. The structures designed with SOI technology have advantages and disadvantages.…”

Section: Introductionmentioning

confidence: 99%

“…1 A stepped polysilicon layer is replaced by the buried oxide layer at the source-side, leading to the optimized surface electric field and a higher breakdown voltage. 6 Three dielectrics are used in this arrangement, a dielectric between the source and gate zones, a dielectric between the drain and drift zones, and another one under the gate and drift zones affecting the breakdown voltage by adding a new peak in the electric field profile. 13 P + buried islands and the p-top layer in the drift zone significantly improve the breakdown voltage.…”

Section: Introductionmentioning

confidence: 99%

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Raised breakdown voltage in a high‐voltage recessed LDD‐SOI by submerged SI3N4

Daneshpajooh

Anvarifard

2022

Int J Numerical Modelling

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A new structure of metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) with lateral double‐diffused MOSFET was introduced based on the silicon‐on‐insulator lightly doped‐drain metal‐oxide‐semiconductor field‐effect‐transistor (SOI‐LDD MOSFET) technology, called recessed silicon nitride lateral‐double diffused silicon‐on‐insulator (RS‐LDD SOI). In the proposed structure, a recession was created on the buried oxide layer and filled with a silicon nitride (SI3N4) layer. Silicon nitride makes the electric field distribution more uniform by modulating the electric field in the drift zone, thereby increasing the breakdown voltage of the proposed structure. The simulation results performed with ATLAS software demonstrated the performance improvement of the proposed structure. Increasing the breakdown voltage by 31% compared to the conventional structure was one of the most important achievements of this work. Also, design considerations were made on the submerged part in the buried oxide, which can be an excellent guide to achieving the optimal performance of the proposed structure.

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Improved SOI LDMOS performance by using a partial stepped polysilicon layer as the buried layer

Cited by 9 publications

References 23 publications

A novel double-gate trench SOI LDMOS with double-dielectric material by TCAD simulation study

A novel double-gate trench SOI LDMOS with double-dielectric material by TCAD simulation study

Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer

Raised breakdown voltage in a high‐voltage recessed LDD‐SOI by submerged SI3N4

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