Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip

Abstract

Virtual channels are an appealing flow control technique for on-chip interconnection networks (NoCs), in that they can potentially avoid deadlock and improve link utilization and network throughput. However, their use in the resource constrained multi-processor system-on-chip (MPSoC) domain is still controversial, due to their significant overhead in terms of area, power and cycle time degradation. This paper proposes a simple yet efficient approach to VC implementation, which results in more area- and power-saving solutions than conventional design techniques. While these latter replicate only buffering resources for each physical link, we replicate the entire switch and prove that our solution is counter intuitively more area/power efficient while potentially operating at higher speeds. This result builds on a well-known principle of logic synthesis for combinational circuits (the area-performance trade-off when inferring a logic function into a gate-level netlist), and proves that when a designer is aware of this, novel architecture design techniques can be conceived

Towards compelling cases for the viability of silicon-nanophotonic technology in future manycore systems

“…Virtual Channel flow control is implemented by replicating the basic switch architecture without VC capabilities three times, based on the approach presented in [71]. This technique results in higher maximum operating speed, better performance and smaller area.…”

ReliNoC: A reliable network for priority-based on-chip communication

“…To address this issue, the use of multiple physicals network on the same chip has been proposed to improve performance and keep traffic classes separate [17] instead of leveraging VCs. Gilabert et al in [1] showed that by replicating switches as many times as the number of VCs, a simple yet efficient implementation can be achieved providing the same (or even better) cycle time at lower area and power.…”

“…We provide two main contributions in this work: first, we propose a new router architecture which distributes the traffic to two different physical channels based on the class of the traffic, which can be either QoS or normal. We completely remove the overhead of VCs by replicating the components inside the switch as proposed in [1]. In addition to [1], we also replicate the links between routers and remove the hardware overhead at input ports.…”

“…We completely remove the overhead of VCs by replicating the components inside the switch as proposed in [1]. In addition to [1], we also replicate the links between routers and remove the hardware overhead at input ports. Note that, other complementary QoS techniques such as circuit switching can be applied on this 2-channel router for guaranteed throughput traffics.…”

“…Since its implementation requires extra buffers, the router power consumption will increase with the number of VCs [14]. Moreover, VCs impose performance overhead due to virtual channel allocators [16], [1].…”