Improvement of Conversion Cycle and Estimation of Capacitor Mismatch in Hybrid Analog-to-Digital Converters Using Flash and Successive Approximation Register

Abstract

This paper presents hybrid analog-to-digital converters (ADCs) using flash ADC and successive approximation register (SAR) ADC for improving conversion speed. The proposed architecture is the flash-hybrid-SAR architecture, which reduces the resolution of the flash ADC in the first stage by 1-bit and increases the resolution of the SAR ADC in the second stage compared to the conventional flash-radix-3-SAR architecture. The proposed ADC consists of the 3-bit flash ADC, 1-trit radix-3 SAR ADC and 4-bit two-bit/cycle SAR ADC to reduce the number of bit in the flash ADC. The proposed flash-hybrid-SAR ADC can reduce by half the number of resistors and comparators in the flash ADC from the conventional 8-bit hybrid flash-radix-3-SAR ADC with the same sampling rate at 142.8 MS/s. We simulated a flash-hybrid-SAR ADC with a capacitor mismatch of ±0.5% under six different conditions. The DNL is within ±0.5 LSB in all conditions when non-idealities other than the capacitor mismatch were eliminated. The INL is also within ±1 LSB in all conditions.