Improvement of PECVD Silicon–Germanium Crystallization for CMOS Compatible MEMS Applications

Abstract

This paper investigates the influence of the electrode spacing, chamber pressure, total gas flow, and H 2 dilution on the crystallinity, resistivity, uniformity, and stress of polycrystalline silicon-germanium ͑poly-SiGe͒ films grown by plasma-enhanced chemical vapor deposition ͑PECVD͒. Boron-doped PECVD SiGe films of 1.6 m thick are deposited on 400 nm chemical vapor deposition layers from SiH 4 , GeH 4 , and B 2 H 6 precursors. The microstructure is verified by transmission electron microscopy and by X-ray diffraction. It was discovered that for constant temperature and deposition rate, the PECVD SiGe microstructure changes from completely amorphous to polycrystalline by increasing the electrode spacing and pressure due to reduced ion bombardment. A process window of an electrode spacing and pressure for the PECVD poly-SiGe deposition is thus identified based on a sheet resistance mapping method. Increasing the total gas flow dramatically improves the within-wafer crystallinity variation and further reduces the resistivity. Increasing the H 2 flow during PECVD shifts the stress from −51 to 17 MPa and further reduces the crystallinity variation over the wafer. In addition, the effect of changing the SiH 4 to GeH 4 ratio and the in situ boron doping by adding B 2 H 6 is also investigated. The findings in this paper are expected to facilitate the use of poly-SiGe in the above complementary metal oxide semiconductor ͑CMOS͒ microelectromechanical system ͑MEMS͒ applications.Polycrystalline silicon-germanium ͑poly-SiGe͒ has been demonstrated to be an excellent material for the fabrication of integrated microsystems in an above complementary metal oxide semiconductor ͑CMOS͒ microelectromechanical system ͑MEMS͒ approach. 1-3 Poly-SiGe has the mechanical and electrical properties similar to polysilicon but can be deposited and crystallized at low temperatures ͑e.g., 450°C for CMOS compatible applications͒. At the same time, poly-SiGe has a relatively high stiffness value ͑around 140 GPa for 60-70 atom % Ge 4 ͒.The deposition rate ͑DR͒ of poly-SiGe can be significantly enhanced by utilizing plasma-enhanced chemical vapor deposition ͑PECVD͒. 5 A typical DR of poly-SiGe deposited using chemical vapor deposition ͑CVD͒ is around 0.6 nm/s after the incubation period, whereas the DR of PECVD deposited poly-SiGe is around 2.3 nm/s and there is no or minimal incubation time. 6 PECVD is therefore the most promising technology in commercializing polySiGe for MEMS applications, where many thick structural/capping layers ͑4-10 m͒ are commonly used. To ensure a good crystalline growth, the bulk PECVD layer is deposited on top of a thin CVD SiGe layer. With this technique, the crystalline grains that form in the slowly grown CVD layer continue up to the PECVD layer. 6 In the meantime, this CVD layer, typically 400 nm, can also be used for the anchor filling of the surface micromachined MEMS structures, where a highly conformal deposition is preferred. The polySiGe films in this paper thus always start with a CVD grown layer.However, di...

Wafer Level Characterization of the Sacrificial HDP Oxide Lateral Etching by Anhydrous Vapor HF with Ethanol Vapor for SiGe MEMS Structures

“…The HDP oxide is deposited as a single stack of 3 μm in 300 s at 400 °C, so there might be some ER variations in different depths of the oxide. The 1 μm SiGe layer consists of a 400 nm chemical vapor deposition (CVD) seed layer and a 600 nm plasma enhanced chemical vapor deposition (PECVD) top layer [4].…”

Physical loss mechanisms for resonant acoustical waves in boron doped poly-SiGe deposited with hydrogen dilution

“…38 The layers were grown on top of SiO 2 , an amorphous material, therefore a 400 nm thick SiGe seed layer was deposited in a CVD tool to obtain a uniform crystallization for the subsequent PECVD growth steps. 38 The layers were grown on top of SiO 2 , an amorphous material, therefore a 400 nm thick SiGe seed layer was deposited in a CVD tool to obtain a uniform crystallization for the subsequent PECVD growth steps.…”

Development, Optimization and Evaluation of a CF4 Pretreatment Process to Remove Unwanted Interfacial Layers in Stacks of CVD and PECVD Polycrystalline Silicon-Germanium for MEMS Applications

“…It has been shown previously that sheet resistance (Rs) measurements are an excellent method of determining the amount and uniformity of polycrystallization in the SiGe stack (7). To determine the influence the interface has on Rs, a reference sample with a 4 µm layer comprising of 2 x 2 µm depositions with an interface between the two depositions, and a sample with a 4 µm layer that was deposited in one single continuous deposition and which therefore had no interface, were compared.…”

“…showing the interfaces and sequential reduction of crystallization Much of this reduced transfer of crystallinity was previously addressed by increasing the PECVD deposition gas flows and adding H 2 , resulting in the improvement shown in Figure 1. This in turn significantly improved the within-wafer uniformity of polycrystallization of the PECVD layers, as determined by reductions in Rs and Rs %σ (7). It was still thought however that removing the interface completely would further improve the transfer of crystallization between the SiGe layers making the process more robust.…”