Improvements to Technology Mapping for LUT-Based FPGAs

Mishchenko, Alan; Chatterjee, Saurav; Brayton, Robert K.

doi:10.1109/tcad.2006.887925

Cited by 115 publications

(76 citation statements)

References 19 publications

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“…Previous work [12] has shown that applying two complementary heuristics, as shown in Figure 3.3, in the given order produces good practical results. The first heuristic (area flow) has a global view and selects logic cones with more shared logic.…”

Section: Area Recoverymentioning

confidence: 96%

“…A standard technique to map into K-input LUTs uses cutenumeration [8][17] [6] [12]. In this approach, the subject graph is traversed in a topological order.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, during area recovery several optimizations are performed to improve the selected mapping. Each pass uses one or more different costfunctions for cut ranking [8] [12].…”

Section: Introductionmentioning

confidence: 99%

“…Heuristic iterative optimization of a mapping discussed in this paper is greedy in the sense that it modifies the representative cuts of one node at a time, in such a way that the area of the current mapping is reduced or remains the same. [7], as implemented in [12]. …”

Section: Introductionmentioning

confidence: 99%

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WireMap

Jang

Chan²,

Chung

et al. 2008

Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays

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This paper presents a new technology mapper, WireMap. The mapper uses an edge flow heuristic to improve the routability of a mapped design. The heuristic is applied during the iterative mapping optimization to reduce the total number of pin-to-pin connections (or edges). The average edge reduction of 9.3% is achieved while maintaining depth and LUT count of state-of-theart technology mapping. Placing and routing the resulting netlists leads to an 8.5% reduction in the total wire length, a 6.0% reduction in minimum channel width, and a 2.3% reduction in critical path delay. Applying WireMap has an additional advantage of reducing an average number of inputs of LUTs without increasing the total LUT count and depth.The percentages of 5-and 6-LUTs in a typical design are reduced, while the percentages of 2-, 3-, and 4-LUTs are increased. These smaller LUTs can be merged into pairs and implemented using the dual output LUT structure found in commercial FPGAs. WireMap leads to 9.4% fewer dual-output LUTs after merging.

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Section: Area Recoverymentioning

confidence: 96%

“…A standard technique to map into K-input LUTs uses cutenumeration [8][17] [6] [12]. In this approach, the subject graph is traversed in a topological order.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, during area recovery several optimizations are performed to improve the selected mapping. Each pass uses one or more different costfunctions for cut ranking [8] [12].…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

WireMap

Jang

Chan²,

Chung

et al. 2008

Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays

Self Cite

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“…This need increases the interest for transistorlevel (or "switch-level") CAD tools for digital VLSI design. Traditional approaches and tools work at the gate level and produce optimized Boolean expressions with respect to constraints such as area, delay and power that are then mapped to platforms such as Programmable Logic Devices (i.e., PLAs, PALs, FPGAs) or standard cells (see, e.g., [18], [10], [3], [20], [9], [17], [1], [6], [19], [4], [8], [5], [25], [28], [23], [24]). The design effort is thus greatly reduced but the area and performance are compromised when compared to what can be achieved by a customized transistor-level approach.…”

Section: Introductionmentioning

confidence: 99%

MOTO-X: A Multiple-Output Transistor-Level Synthesis CAD Tool

Kagaris

2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Transistor count minimization is an important goal as VLSI technology approaches its technical and physical limits. In this work, we present a CAD synthesis tool that tries to minimize the number of transistors required to implement a given multiple-output logic function. The proposed transistor-level synthesis approach goes beyond the traditional series-parallel design style and allows for extensive bridging. It starts from a sum-ofproducts expression for each output, allowing also for don't care terms, and produces a transistor network with a small number of transistors to implement all outputs jointly under a userspecified bound on the number of transistors in series to avoid long charge/discharge paths. Experimental results on previously examined multi-output functions and case studies (Full Adder, Gray/Binary Counter, Seven-Segment Display) demonstrate the benefit of the approach.

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Applications

2016

Boolean Circuit Rewiring

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Improvements to Technology Mapping for LUT-Based FPGAs

Abstract: The paper presents several improvements to state-of-theart

Cited by 115 publications

References 19 publications

WireMap

WireMap

MOTO-X: A Multiple-Output Transistor-Level Synthesis CAD Tool

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