Improving accuracy of on-chip diagnosis via incremental learning

Ren, Xuanle; Martin, M.C.; Blanton, R. D.

doi:10.1109/vts.2015.7116280

Cited by 14 publications

(6 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Later on, dynamic patterns will also be used to sensitize delay faults. Note that this number (16) increases exponentially with the number of inputs of a gate. Similarly, the length of each training data (as shown in Figure 2) as well as the number of data increases accordingly.…”

Section: Resultsmentioning

confidence: 99%

“…In [15], authors describe an approach to identify bridge defects from a population of diagnosed defects by using a combination of effective rules and a decision-tree-based classifier. In [16], authors improve on-chip diagnosis resolution with a modified k-nearest neighbors classifier that is updated with real-time failure data. In [17], volume diagnosis resolution is improved with a Bayesian classifier that identifies the actual candidates based on their layout properties.…”

Section: State Of the Art And Motivationsmentioning

confidence: 99%

See 1 more Smart Citation

Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip

Mhamdi

Virazel

Girard

et al. 2019

2019 IEEE 25th International Symposium on on-Line Testing and Robust System Design (IOLTS)

View full text Add to dashboard Cite

In critical (e.g. automotive) applications, Systems-on-Chip (SoC) failures that occurred during mission mode (in the field) are the most critical since they may lead to catastrophic effects. In this context, diagnosis is crucial in order to establish the root cause of observed failures with the best accuracy. With the advent of very deep submicron technologies (i.e. 7 nm), achieving such level of accuracy will become more and more difficult with today's intra-cell diagnosis tools based on effectcause or cause-effect paradigms. This will compromise the success of subsequent Physical Failure Analysis (PFA) done on defective SoCs. Machine Learning (ML) is now used in numerous classification problems where the knowledge on some data can be used to classify a new instance of such data. In particular, several ML-based solutions exist to address volume diagnosis for yield improvement. These learning-guided diagnosis approaches start from an existing set of defect candidates and try to minimize this set (eliminate bad candidates) owing to the use of ML tools and numerous data collected during production test (e.g. thousands of failed chips with candidates correctly labeled). Although efficient in volume diagnosis, these approaches cannot be used to identify the root cause of failures in customer returns, since only one failed chip is investigated in this case, with no information about the defective behavior of some other similar chips used in the same conditions (environment, workload, etc.). In this paper, we propose a new learning-guided approach for diagnosis of mission mode failures in customer returns. The proposed approach directly produces a minimum set of good candidates derived from the application of the learning-guided intra-cell diagnosis flow. Results obtained on a set of benchmark circuits, and comparison with a commercial intra-cell diagnosis tool, show the feasibility, effectiveness and accuracy of the proposed approach.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: State Of the Art And Motivationsmentioning

confidence: 99%

Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip

Mhamdi

Virazel

Girard

et al. 2019

2019 IEEE 25th International Symposium on on-Line Testing and Robust System Design (IOLTS)

View full text Add to dashboard Cite

show abstract

“…In [16], authors describe an approach to identify bridge defects from a population of diagnosed defects by using a combination of effective rules and a decision-treebased classifier. In [17], authors improve on-chip diagnosis resolution with a modified k-nearest neighbors classifier that is updated with real-time failure data. In [18], volume diagnosis resolution is improved with a Bayesian classifier that identifies the actual candidates based on their layout properties.…”

Section: State Of the Art And Motivationsmentioning

confidence: 99%

Cell-Aware Defect Diagnosis of Customer Returns Based on Supervised Learning

Mhamdi

Girard

Virazel

et al. 2020

IEEE Trans. Device Mater. Relib.

View full text Add to dashboard Cite

HAL is a multidisciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L'archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

show abstract

“…To demonstrate the viability of SLIC, several projects have been initiated [19][20][21][22][23][24][25][26][27][28][29][30][31][32]. A brief overview of some of these projects, which span from applications, architectures, and circuits, are presented here in this section.…”

Section: Slic Projectsmentioning

confidence: 99%

Statistical learning in chip (SLIC)

Blanton¹,

Li²,

Mai³

et al. 2015

2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

View full text Add to dashboard Cite

Despite best efforts, integrated systems are "born" (manufactured) with a unique 'personality' that stems from our inability to precisely fabricate their underlying circuits, and create software a priori for controlling the resulting uncertainty. It is possible to use sophisticated test methods to identify the bestperforming systems but this would result in unacceptable yields and correspondingly high costs. The system personality is further shaped by its environment (e.g., temperature, noise and supply voltage) and usage (i.e., the frequency and type of applications executed), and since both can fluctuate over time, so can the system's personality. Systems also "grow old" and degrade due to various wear-out mechanisms (e.g., negative-bias temperature instability), and unexpectedly due to various early-life failure sources. These "nature and nurture" influences make it extremely difficult to design a system that will operate optimally for all possible personalities. To address this challenge, we propose to develop statistical learning in-chip (SLIC). SLIC is a holistic approach to integrated system design based on continuously learning key personality traits on-line, for selfevolving a system to a state that optimizes performance hierarchically across the circuit, platform, and application levels. SLIC will not only optimize integrated-system performance but also reduce costs through yield enhancement since systems that would have before been deemed to have weak personalities (unreliable, faulty, etc.) can now be recovered through the use of SLIC.

show abstract

Improving accuracy of on-chip diagnosis via incremental learning

Cited by 14 publications

References 21 publications

Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip

Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip

Cell-Aware Defect Diagnosis of Customer Returns Based on Supervised Learning

Statistical learning in chip (SLIC)

Contact Info

Product

Resources

About