Improving and optimizing reliability in future technologies with high-&amp;#x03BA; dielectrics

Linder, B.; Cartier, E.; Krishnan, Siddarth; Wu, E.

doi:10.1109/vlsi-tsa.2013.6545622

Cited by 4 publications

(4 citation statements)

References 3 publications

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“…The native oxide thickness (t IL ) is considered for 3 values namely, 0.7 nm, 0.9 nm and 1.3 nm. The breakdown electric field is represented as [70],…”

Section: Dielectric Technology For Mtm Devices: Reliability Aspectmentioning

confidence: 99%

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Chowdhury,

Sarkar,

Mahapatra

et al. 2024

Phys. Scr.

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The progress in IC miniaturization dictated by Moore’s Law has taken a leap from mere circuit integration to IoT enabled System-on-Chip (SoC) deployments. Such systems are connoted by contemporary advancements in the semiconductor industry roadmaps namely, ‘More-Moore’ and ‘More-than-Moore’ (MtM). For meaningful integration of digital and non-digital blocks, a power performance tradeoff is essential for maximum and fruitful utilization of the silicon area. Using the techniques under the MtM nomenclature allows the use of unconventional steep slope devices like Tunneling FETs, Negative Capacitance (NC) FETs, Gate-all-around FETs (GAA) and FinFETs etc., which can exhibit reasonable performance with lower supply voltages. Following the Device Technology Co-optimization (DTCO) and System Technology Co optimization (STCO) the advanced 3D heterogenous integration technologies allow sensors, analog/mixed signal and passive components to be assimilated within the same package as the CMOS blocks. Appropriate device engineering techniques like multi-gate architectures, vertical stacking transistors, compound semiconductors and alternate carrier transport phenomena are required to improve the current drive and scaling performance of advanced CMOS devices. CMOS based codesign is essential to realize new topologies for energy economical computation, sensing and information processing as the beyond CMOS steep slope devices are independently incapable of replacing conventional bulk CMOS devices. This article presents a detailed qualitative review of the various aspects of MtM beyond CMOS steep slope switches and their prospective integration technologies. For system level integration, various aspects of device performance and optimizations, related device-circuit interactions, dielectric technologies at the advance nanometer nodes have been probed into. Additionally, novel circuit topologies, synthesis algorithms and processor level performance evaluation using steep slope switches have been investigated. An exclusive compact overview for contemporary insights into integrated device-system development methodology and its performance evaluation is presented.

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“…The native oxide thickness (t IL ) is considered for 3 values namely, 0.7 nm, 0.9 nm and 1.3 nm. The breakdown electric field is represented as [70],…”

Section: Dielectric Technology For Mtm Devices: Reliability Aspectmentioning

confidence: 99%

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Chowdhury,

Sarkar,

Mahapatra

et al. 2024

Phys. Scr.

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“…Many important experimental findings and different breakdown models have been reported regarding the first BD and progressive BD statistics and TDDB voltage and temperature dependence [17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34]. In particular, the impact of stress pattern (DC vs. AC) on BD characteristics has been clearly identified for high-/SiO 2 nFETs in contrast to single-layer SiO 2 [19,26].…”

Section: Introductionmentioning

confidence: 99%

Recent advances in dielectric breakdown of modern gate dielectrics

Suñé

2013

2013 IEEE International Integrated Reliability Workshop Final Report

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In this talk, we first review the first BD and post BD statistics of high-k/SiO 2 bilayer films (or high-stacks) by delineating similarities and differences from SiO 2 singlelayer films. Then, we will discuss the recent progress on TDDB voltage and temperature dependence in a two-step model of species-release and reaction process. This model is found to be applicable to both SiO 2 and high-stacks (pFET inversion mode) and provide a sound physical picture for overall BD process. Finally, we will highlight the challenges in AC TDDB reliability, specifically related to nFET inversion mode of high-k stacks.

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“…It is well-known that in addition to a "permanent" degradation, there is a large recoverable degradation component [7] that gets larger as the delay between stress and measure is shorter. This recoverable component, when it is taken into account, is often treated as a source for lifetime extension [1][2][3][4][5][6][8][9][10][11][12]. In other words, the recovery buys margin in measured lifetime.…”

mentioning

confidence: 99%

“…In other words, the recovery buys margin in measured lifetime. BTl degradations mostly manifest as threshold voltage (VTH) increase, leading to frequency degradation in ring oscillator (RO) "test" circuits [8][9][10][11][12]. This RO degradation is the most "circuit relevant" BTl guidance for circuit designers even though RO patterns are poor representations of random digital logic.…”

mentioning

confidence: 99%