Improving cache performance with balanced tag and data paths

Abstract

HoneSty Y o u n g ~ Shauchi O n g CS D e p a r t m e n t I B M A l m a d e n Research C e n t e r San Jose, C A 95120 { y o u n g , o n g } © a l m a d e n , ibm. com AbstractThere are two concurrent paths in a typical cache access -one through the data array and the other through the tag array. The path through the data array drives the selected set out of the array. The path through the tag array determines cache hit/miss and, for set-associative caches, selects the appropriate line from within the selected set. In both directmapped and set-associative caches, the path through the tag array is significantly longer than that through the data array. In this paper, we propose a path balancing technique to help match the delays of the tag and data paths. The basic idea behind this technique is to employ a separate subset of the tag array to decouple the one-to-one relationship between address tags and cache lines so as to achieve a design that provides higher performance. Performance evaluation using both TPC-C and SPEC92 benchmarks shows that this path balancing technique offers impressive improvements in overall system performance over conventional cache designs. For TPC-C, improvements in the range of 6% to 28% are possible.

Reducing cache misses through programmable decoders

“…The B-Cache incorporates three tag bits into the programmable decoder; therefore, the tag length is reduced by 3 bits, which reduces the tag-side access time. However, we do not claim this access time reduction, since the data and tag path may already be balanced [Peir et al 1996], so that the data side would be on the critical path.…”

“…The critical path of a conventional direct-mapped cache normally resides on the tag side instead of the data side [Peir et al 1996]. The B-Cache incorporates three tag bits into the programmable decoder; therefore, the tag length is reduced by 3 bits, which reduces the tag-side access time.…”