Improving cache performance with balanced tag and data paths

Peir, Jih-Kwon; Hsu, Windsor W.; Young, Honesty C.; Ong, S.

doi:10.1145/237090.237202

Cited by 13 publications

(2 citation statements)

References 22 publications

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“…The B-Cache incorporates three tag bits into the PD; therefore the tag length is reduced by three bits, which reduces the tag side access time. However, we do not claim this access time reduction since the data and tag path may already be balanced [19] so that the data side would be on the critical path.…”

Section: Timing Analysismentioning

confidence: 86%

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Balanced Cache

Zhang

2006

SIGARCH Comput. Archit. News

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Level one cache normally resides on a processor's critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared with same sized set-associative caches due to nonuniform accesses to the cache sets, which generate more conflict misses in some sets while other sets are underutilized. We propose a technique to reduce the miss rate of direct mapped caches through balancing the accesses to cache sets. We increase the decoder length and thus reduce the accesses to heavily used sets without dynamically detecting the cache set usage information. We introduce a replacement policy to direct-mapped cache design and increase the access to the underutilized cache sets with the help of programmable decoders. On average, the proposed balanced cache, or B-Cache, achieves 64.5% and 37.8% miss rate reductions on all 26 SPEC2K benchmarks for the instruction and data caches, respectively. This translates into an average IPC improvement of 5.9%. The B-Cache consumes 10.5% more power per access but exhibits 2% total memory access related energy saving due to the miss rate reductions and hence the reduction to applications' execution time. Compared with previous techniques that aim at reducing the miss rate of direct-mapped caches, our technique requires only one cycle to access all cache hits and has the same access time of a direct-mapped cache.

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Section: Timing Analysismentioning

confidence: 86%

“…The critical path of a conventional direct-mapped cache normally resides on the tag side instead of the data side [19]. The B-Cache incorporates three tag bits into the PD; therefore the tag length is reduced by three bits, which reduces the tag side access time.…”

Section: Timing Analysismentioning

confidence: 99%