Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression

Abstract

This paper proposes a new test data compression/decompression method for systems-on-a-chip. The method is based on analyzing the factors that influencetest parameters: compression ratio, area overhead and test application time. To improve compression ratio, the new method is based on a Variable-length Input Huffman Coding (VIHC), which fully exploits the type and length of the patterns, as well as a novel mapping and reordering algorithm proposed in a pre-processing step. The new VIHC algorithm is combined with a novel parallel on-chip decoder that simultaneously leads to low test application time and low area overhead. It is shown that, unlike three previous approaches [2, 3, 10] which reduce some test parameters at the expense of the others, the proposed method is capable of improving all the three parameters simultaneously. For example, the proposed method leads to similar or better compression ratio when compared to frequency directed run-length coding [2], however with lower area overhead and test application time. Similarly, there is comparable or lower area overhead and test application time with respect to Golomb coding [3], with improvements in compression ratio. Finally, there is similar or improved test application time when compared to selective coding [10], with reductions in compression ratio and significantly lower area overhead. An experimental comparison on benchmark circuits validates the proposed method.

Efficient test compression technique based on block merging

“…Golomb [4], FDR [5], ALT-FDR [6] EFDR [7], SHC [8], VIHC [9], RL-HC [10], and 9C [12]. It should be noted that SHC [8], VIHC [9] and RL-HC [10] are test-data dependent while the other techniques are test independent.…”

“…It should be noted that SHC [8], VIHC [9] and RL-HC [10] are test-data dependent while the other techniques are test independent.…”

On combining pinpoint test set relaxation and run-length codes for reducing test data volume

“…The column of "nonpinpoint" shows the results without using the gain table, i.e., the procedure tries to change all 1s in the test set to 0s without notice. The following columns gives results of EFDR coding [9], variable-length Huffman coding [14], RESPIN++ [15], and XOR network [12]. For many circuits, the proposed method showed the highest performance on compression.…”

“…Large test data volumes lead to an increase in testing time and the need for multiple ATE channel reloads, either from workstations across a network or from slow hard disks. As a result, a number of techniques have recently been presented in the literature to reduce test data volume, and thereby reduce test cost [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15]. One such technique is test compaction, which relies on ATPG techniques to generate a small test set with maximum fault coverage [1,2,3].…”

Efficient space/time compression to reduce test data volume and testing time for IP cores

“…An on-chip decoder is used for pattern decompression to generate T D from T E during pattern application [3,5,19]. Such techniques are typically based on run-length codes and their variants, e.g., frequency-directed run-length (FDR) codes.…”