Improving Driving Current with High-Efficiency Landing Pads Technique for Reduced Parasitic Resistance in Gate-All-Around Si Nanosheet Devices

Abstract

In order to improve the driving ability of vertically-stacked gate-all-around (GAA) Si nanosheets (NSs) devices, a high-efficiency hybrid pattern technique with the SiNx spacer-image transfer and conventional photolithography pattern was proposed and implemented to form size-enlarged landing pads (LPs) on nanometer-scale fins at the same time, which increase the volumes of electrical conductance pathway between NS channel and source and drain (SD) electrodes with high process efficiency and compatibility with traditional mass production technology. Due to introduced new structures, the parasitic resistance of the devices is reduced by 99.8% compared with those w./o. LPs. Therefore, ~3 times and ~2 times driving current enhancements for 500 nm gate length n-type and p-type MOSFETs are obtained, respectively. The results indicate the proposed GAA NS FET fabrication process with LPs by high-efficiency hybrid pattern technique a promising solution for improving the device driving ability for stacked GAA Si NSs devices in future.

New structure transistors for advanced technology node CMOS ICs

“…[ 35 ] obtained a uniform inner spacer by using a high-precision controllable silicon nitride inner spacer structure that was prepared using an inductively coupled plasma tool and a new gas mixture of CH 2 F 2 /CH 4 /O 2 /Ar; they also developed quasi-atomic layer etching techniques with an accuracy of ∼0.3 nm/cycle. In addition, because of the poor-quality conductance pathway between the stacked NS channels and SD electrodes formed simultaneously by complex selective SiGe or Si epitaxy processing of the bottom substrate and the separated multi-layer Si NSs, high parasitic resistances often occur, causing the operating currents to degrade [ 36 ].…”

DC Characteristics and Dynamic Properties of Multi-Channel Nanosheet MOSFETs with and without Tungsten Metal Sidewall for Sub-3-nm Technological Nodes

“…However, when the number of channel increases, the source/drain (S/D) resistance and the parasitic capacitance are increased simultaneously owing to the increased height of highly doped S/D, which results in a significantly smaller current density in the bottom channel. 8,9 To achieve better performances, such as the on-current, 10,11 the gate delay, 11,12 the noise margin, 10 for the NS devices, researchers have studied the geometry effect of the channel, [13][14][15] the workfunction of the metal gate, 16 the metal source/drain, 11 the thermal performance, 17 the high-efficiency landing pads technique, 18 and so on.…”