Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems

Abstract

Abstract-This paper presents a modelling approach for the timing behavior of real-time embedded systems (RTES) in early design phases. The model focuses on multicore processorsaccepted as the next computing platform for RTES -and in particular it predicts the contention tasks suffer in the access to multicore on-chip shared resources. The model presents the key properties of not requiring the application's source code or binary and having high-accuracy and low overhead. The former is of paramount importance in those common scenarios in which several software suppliers work in parallel implementing different applications for a system integrator, subject to different intellectual property (IP) constraints. Our model helps reducing the risk of exceeding the assigned budgets for each application in late design stages and its associated costs.

An extensible framework for multicore response time analysis

“…The main problem with non-blocking caches is that the miss status holding registers (MSHRs), special hardware registers which track the status of outstanding cache-misses, can be a significant source of contention (Valsan et al 2016). Trilla et al (2016) proposed a timing model to predict the performance of applications at an early design stage. Their approach is based on generating an execution profile for each application that allows contention analysis on the shared processor resources.…”

Modelling bus contention during system early design stages

“…However, due to the lack of timing information, the timing verification process cannot be carried out. Recently, this problem has been alleviated by light-weight a contention model that derives estimates to applications' execution time for multicore systems [7]. That model takes as input an execution profile (EP) of the application that comprises information extracted from its execution in isolation (e.g.…”

“…For instance, roro is implemented in the ARM Cortex-A9 [24] and the NXP MSC8122 [21] processors. In particular the main contributions of this paper are: 1) We make an in-depth analysis of the bus model proposed in [7] for roro. We show the main assumptions made by that bus model and analyze the inaccuracies they cause.…”

“…This can result in having applications at LDP that do not fit their budget, causing significant costs: either the system integrator has to change the schedule of applications granting more budget to those missing their deadlines, or the SWPs are required to change their applications to fit their assigned budget. As part of our analysis we provide insights on why the model in [7] also works for fifo. In particular we show how expected contention is higher with fifo than with roro.…”

“…In particular we show how expected contention is higher with fifo than with roro. 2) We propose a new bus model that captures the main inaccuracies of that in [7]. First, unlike [7], our model captures the fact that buses support different request types and each can take a different latency.…”