Improving Energy and Performance with Spintronics Caches in Multicore Systems

Tuohy, William; Ma, Cong; Nandkar, Pushkar Shridhar; Borse, Nishant Ashok; Lilja, David J.

doi:10.1007/978-3-319-14313-2_24

Cited by 1 publication

(2 citation statements)

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“…A method to match the bandwidth between the CPU and the L1 cache is needed that does not also increase cache energy consumption significantly. Augmenting the STT‐MRAM L1 with a small fully associative CMOS L0 cache was investigated in [9] and found to be an effective method to restore the performance lost to higher write latency. The L0 cache acts as a write‐merging buffer, translating single‐word writes from the CPU into cache line writes to the L1.…”

Section: Performance Energy and Scalabilitymentioning

confidence: 99%

“…This structure also benefits cache dynamic energy consumption, since it is so small that both its static and dynamic energies use are quite low. This is an extension of the analysis in [9], which analysed the effectiveness of a small L0 of various sizes compared with a simpler two-level CMOS hierarchy. The contributions of this paper include: • A detailed analysis of the impact of high write latency at the L1 cache level including the tradeoff between read and write energies and latencies of STT-MRAM caches.…”

Section: Introductionmentioning

confidence: 99%

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Impact of spintronic memory on multicore cache hierarchy design

Tuohy

Lilja

2017

IET Computers & Digital Techniques

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Spintronic memory [spin-transfer torque-magnetic random access memory (STT-MRAM)] is an attractive alternative technology to CMOS since it offers higher density and virtually no leakage current. Spintronic memory continues to require higher write energy, however, presenting a challenge to memory hierarchy design when energy consumption is a concern. This study motivates the use of STT-MRAM for the first-level caches of a multicore processor to reduce energy consumption without significantly degrading the performance. The large STT-MRAM first-level cache implementation saves leakage power. Moreover, the use of small level-0 cache regains the performance drop due to STT-MRAM long write latencies. The combination of both reduces the energy-delay product by 65% on average compared with CMOS baseline. The proposed STT hierarchy also shows good scalability over the CMOS with a few benchmarks which scale significantly better. The PARSEC and Splash2 benchmark suites are analysed running on a modern multicore platform, comparing performance, energy consumption and scalability of the spintronic cache system to a CMOS design.

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Section: Performance Energy and Scalabilitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%