Improving Energy Efficiency in Memory-constrained Applications Using Core-specific Power Control

Abstract

Power is increasingly the limiting factor in High Performance Computing (HPC) at Exascale and will continue to influence future advancements in supercomputing. Recent processors equipped with on-board hardware counters allow real time monitoring of operating conditions such as energy and temperature, in addition to performance measures such as instructions retired and memory accesses. An experimental memory study presented on modern CPU architectures, Intel Sandybridge and Haswell, identifies a metric, TORo core, that detects bandwidth saturation and increased latency. TORo core is used to construct a dynamic policy applied at coarse and fine-grained levels to modulate per-core power controls on Haswell machines. The coarse and fine-grained application of dynamic policy shows best energy savings of 32.1% and 19.5% with a 2% slowdown in both cases. On average for six MPI applications, the fine-grained dynamic policy speeds execution by 1% while the coarse-grained application results in a 3% slowdown. Energy savings through frequency reduction not only provide cost advantages, they also reduce resource contention and create additional thermal headroom for non-throttled cores improving performance.

Investigating power capping toward energy‐efficient scientific applications

“…Kimura et al examine slack in unbalanced work distributions generated from distributed DAG executions and use DVFS to adapt the execution speed for tasks in order to balance the execution without increasing the overall execution time. Bhalachandra et al use several system metrics (eg, TOR Table‐Of‐Requests occupancy) to characterize memory behavior and apply coarse‐grained and fine‐grained power policies implemented using DVFS. They demonstrate substantial power savings on mini‐apps with minimal performance change using these system metrics.…”

Cuttlefish: Library for Achieving Energy Efficiency in Multicore Parallel Programs

“…DVFS is supported by both AMD and Intel processors. It has been the primary choice to control processor frequency in several studies [4,5,16,17,23,27,29,39,41,47]. In the past, processors provided only chip-level DVFS where a frequency change affected all the cores.…”

“…The approaches that target the Message Passing Interface (MPI) applications mainly involve mitigation of workload imbalance between the process (slack) [4,16,29,41]. Other MPI-centric solutions address cases where the processor cores wait on the memory or network [5,22,26,43,48,49]. Concurrency throttling has been widely used by adapting the thread count in OpenMP programs that are memory-constrained to reduce power consumption [12,13,31,37].…”

FlexClock: Generic Clock Reconfiguration for Low-end IoT Devices

“…On the custom chip level there are still significant advancements being made to further reduce energy consumption of chip-internal component primitives such as clock gates [20]. DVFS slowly trickles down to smaller, more constrained target devices, stretching across data centers [4], personal computers, laptops and smartphones to wireless sensor nodes [12,2]. With D 2 VFS , Ahmed et al [1] recently proposed a discrete DVFS variant that moves this further onto the intermittent device class.…”