Improving energy efficiency of DRAM by exploiting half page row access

Ha, Heonjae; Pedram, Ardavan; Richardson, Stephen; Kvatinsky, Shahar; Horowitz, Mark

doi:10.1109/micro.2016.7783730

Cited by 13 publications

(18 citation statements)

References 27 publications

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“…Moreover, the precharge and activation operations triggered by the row buffer conflict increase energy consumption. A variety of techniques [8,9,[16][17][18] have been proposed to address the row buffer conflict problem by improving the row buffer utilization. Shao and Davis [16] proposed to group the requests targeting the same rows to increase row buffer hit rate and utilization.…”

Section: Role Of the Row Buffermentioning

confidence: 99%

“…The TCM addressed this problem by grouping the applications by its characteristics of memory access, and the spatial locality is preserved [9] . Also, to reduce the granularity of memory operations, Half Page is leveraged to enable the row buffer to contain data from two rows [8] .…”

Section: Role Of the Row Buffermentioning

confidence: 99%

“…Extensive recent researches have been conducted on mitigating the "memory wall" problem via reducing memory latency. Various factors can affect the memory latencies, such as DRAM refresh [4][5][6][7] , row buffer overfetch [2,8] , and interference between competing processes [9] . In fact, the increase in memory capacity can hurt memory latency [3] .…”

Section: Introductionmentioning

confidence: 99%

“…To improve the row buffer utilization, various approaches have been proposed. Some works suggest to maximize the utilization of the row buffer by scheduling [2] , or group the memory requests by the targeting rows at the memory controller [8] . Other works try to mitigate the latencies by taking advantage of DRAM characteristics that accessing the rows near the row buffer incurs less latencies [3] .…”

Section: Introductionmentioning

confidence: 99%

“…Other works try to mitigate the latencies by taking advantage of DRAM characteristics that accessing the rows near the row buffer incurs less latencies [3] . Similarly, the halfpage [8] takes advantage of the new feature of DDR4 [15] to reduce the granularity of row activation and precharge, resulting in more valuable data being kept the row buffer.…”

Section: Introductionmentioning

confidence: 99%

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RBC: A memory architecture for improved performance and energy efficiency

Liu

Zhou

Huang

et al. 2021

Tinshhua Sci. Technol.

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DRAM-based memory suffers from increasing row buffer conflicts, which causes significant performance degradation and power consumption. As memory capacity increases, the overheads of the row buffer conflict are increasingly worse as increasing bitline length, which results in high row activation and precharge latencies. In this work, we propose a practical approach called Row Buffer Cache (RBC) to mitigate row buffer conflict overheads efficiently. At the core of our proposed RBC architecture, the rows with good spatial locality are cached and protected, which are exempted from being interrupted by the accesses for rows with poor locality. Such an RBC architecture significantly reduces the overheads of performance and energy caused by row activation and precharge, and thus improves overall system performance and energy efficiency. We evaluate RBC architecture using SPEC CPU2006 on a DDR4 memory compared to a commodity baseline memory system. Results show that RBC improves the overall performance by up to 2:24 (16:1% on average) and reduces the memory energy by up to 68:2% (23:6% on average) for single-core simulations. For multi-core simulations, RBC increases the overall performance by up to 1:55 (17% on average) and reduces memory energy consumption by up to 35:4% (21:3% on average).

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