In this paper, we show our 165 Gbps data link layer processor for wireless communication in the terahertz band. The design utilizes interleaved Reed-Solomon codes with dedicated link adaptation, fragmentation, aggregation, and hybrid-automatic-repeat-request. The main advantage is the low-chip area required to fabricate the processor, which is at least two times lower than the area of low-density paritycheck decoders. Surprisingly, our solution loses only ∼1 dB gain when compared to high-speed low-density parity-check decoders. Moreover, with only 2.38 pJ/bit of energy consumption at 0.8 V, one of the best results in the class of comparable implementations has been achieved. Alongside, we show our vision of a complete 100 Gbps wireless transceiver, including radio frequency frontend and baseband processing. For the baseband realization, we propose a parallel sequence spread spectrum and channel combining at the baseband level. Challenges to high-speed wireless transmission at the terahertz band are addressed as well. To the authors' best knowledge, it is one of the first data link layer implementations that deal with a data rate of ≥ 100 Gbps. INDEX TERMS 100 Gbps wireless, terahertz communication, Reed-Solomon coding, data link layer. The associate editor coordinating the review of this manuscript and approving it for publication was Khursheed Aurangzeb. FIGURE 1. Discussed wireless radio-transceiver system. and baseband implementations. Fig. 1 depicts the architecture of the discussed wireless radio-transceiver. A. CHALLENGES TO HIGH-SPEED WIRELESS COMMUNICATIONS Ultra-high speed wireless systems require either very high bandwidth or very high bandwidth efficiency. In cellular architectures like LTE or 5G high bandwidth efficiency is in the focus. This is due to the limited bandwidth in the available radio bands. Increasing the bandwidth efficiency requires a corresponding increase in signal processing power