Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations

Ness, Drew C.; Hescott, C.J.; Lilja, David J.

doi:10.1109/nanoarch.2007.4400857

Cited by 8 publications

(7 citation statements)

References 54 publications

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“…Alternatively, the single exponential current model given in [22] may also be used. Researchers in [23,24] mention that the single pole model can be replaced by double exponential current pulse model for SEUs without loss of generality. The double pole representation has been used here as an approximation to waveforms seen in mixed-mode simulations.…”

Section: Analysis Single Event Crosstalkmentioning

confidence: 99%

Single Event Soft Error Mechanisms

Sayıl

2016

Soft Error Mechanisms, Modeling and Mitigation

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It has been reported that advanced processors with large multimegabit-embedded SRAM can easily have soft failure rates in excess of 50,000 FIT at terrestrial level [1]. The same error rate can also be achieved for standard high-density ASIC designs at 90 nm and below in [2].For single-chip consumer applications, this error rate may not still be important for most designers, but for high-reliability systems composed of multi-chip assemblies such a rate becomes intolerable [1]. Hence, for mission-critical or high-reliability applications such as military, avionics [3], medical systems [4], etc., other sources for such errors also need to be included in reliability analysis in addition to SETs. These additional error sources include SE soft delays [5], radiation induced clock jitters and clock pulses [6], SE crosstalk noise pulses [7][8][9], and finally the SE crosstalk delay [10] that has been reported relatively recently.All these errors occur under specific conditions: Soft delay effect occurs when high-energy particle hits the drain node of a CMOS gate's transistor while signal at the output is transitioning. SE clock jitter occurs when particles inject charge onto clock circuit nodes during clock edge present. An energetic particle strike on clock circuit nodes can also create a "false clock pulse" which can be interpreted as a legitimate clock pulse. At last, the SE crosstalk noise and crosstalk delay effects occur via interconnect cross-coupling. The interconnect coupling effects can cause SETs to contaminate electronically unrelated circuit paths which can in turn increase the "SE susceptibility" of CMOS circuits.With newer technologies the severity of these mechanisms increase as transistor sizes reduces and working frequencies increase.

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Section: Analysis Single Event Crosstalkmentioning

confidence: 99%

Single Event Soft Error Mechanisms

Sayıl

2016

Soft Error Mechanisms, Modeling and Mitigation

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“…The methods implemented in [ 22 ] suggested the use of screening experiment based on statistical approach, that is, the Plackett Burman approach. The method can identify and estimate the effect of key factors towards SEU tolerance.…”

Section: Measurement and Modeling Of An Seumentioning

confidence: 99%

“…Subsequently, the statistical outcomes can support the accuracy of the reliability estimation, as well as identify additional properties of Q crit measurements at the circuit level. In [ 22 ] several technology parameters have been identified and grouped into larger categories such as voltages, parameter sizing, current injection models, and operating parameters.…”

Section: Measurement and Modeling Of An Seumentioning

confidence: 99%

Single-Event-Upset Sensitivity Analysis on Low-Swing Drivers

Mahyuddin

Russell

2014

The Scientific World Journal

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Technology scaling relies on reduced nodal capacitances and lower voltages in order to improve performance and power consumption, resulting in significant increase in layout density, thus making these submicron technologies more susceptible to soft errors. Previous analysis indicates a significant improvement in SEU tolerance of the driver when the bias current is injected into the circuit but results in increase of power dissipation. Subsequently, other alternatives are considered. The impact of transistor sizes and temperature on SEU tolerance is tested. Results indicate no significant changes in Q crit when the effective transistor length is increased by 10%, but there is an improvement when high temperature and high bias currents are applied. However, this is due to other process parameters that are temperature dependent, which contribute to the sharp increase in Q crit. It is found that, with temperature, there is no clear factor that can justify the direct impact of temperature on the SEU tolerance. Thus, in order to improve the SEU tolerance, high bias currents are still considered to be the most effective method in improving the SEU sensitivity. However, good trade-off is required for the low-swing driver in order to meet the reliability target with minimal power overhead.

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“…Alternatively, the single exponential current model given in [17] may also be used. Researchers in [15,18] mention that the single pole model can be replaced by double exponential current pulse model for SEUs without loss of generality. In this work, the double pole representation has been used as an approximation to waveforms seen in mixed-mode simulations.…”

Section: Introductionmentioning

confidence: 99%

Single event crosstalk prediction in nanometer technologies

Sayıl

Boorla

2011

Analog Integr Circ Sig Process

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As CMOS technology continues to scale down, circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. On the other hand, coupling effects among interconnects can cause single event transients to contaminate electronically unrelated circuit paths which may increase the SE susceptibility of CMOS circuits. The coupling effects among interconnects need to be considered in single event hardening, modeling and analysis of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. This work, for the first time, proposes an SE crosstalk noise estimation method for use in design automation tools. The proposed method uses an accurate 4-p model for interconnect and correctly models the effect of non-switching aggressors as well as aggressor tree branches noting the resistive shielding effect. The SE crosstalk noise expressions derived show very good results in comparison to HSPICE results. Results show that average error for noise peak is about 5.2% while allowing for very fast analysis in comparison to HSPICE.

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Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations

Cited by 8 publications

References 54 publications

Single Event Soft Error Mechanisms

Single Event Soft Error Mechanisms

Single-Event-Upset Sensitivity Analysis on Low-Swing Drivers

Single event crosstalk prediction in nanometer technologies

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