Improving performance of codes with large/irregular stride memory access patterns via high performance reconfigurable computers

Abed, K.H.; Morris, Gerald R.

doi:10.1016/j.jpdc.2012.07.011

Cited by 1 publication

(4 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…When the data size exceeds the cache limits of the GPP then the GPP performance suffers. See [24] for the supporting research. Notice that several of the hardware cases show a nearly threefold speedup over software.…”

Section: J Results 1) Description Of Test Problemsmentioning

confidence: 99%

“…Direct memory access (DMA) is used to move data between the Xeon memory and MAP memory. In addition, the MAP processor has a streaming DMA capability, and an inter/intra-FPGA streaming capability that allows overlapping communication and computation [19], [20], [21], [22], [23], [24], [25].…”

Section: Description Of Target Hprcmentioning

confidence: 99%

“…Memory access patterns -If a candidate kernel has large or irregular stride memory access patterns, then it is more likely to do well on an FPGA, which does not depend upon the memory access patterns like a cachebased GPP. See [24] for a more detailed discussion of this issue.…”

Section: B Fpga Design Boundarymentioning

confidence: 99%

“…Control/memory vs. compute intensive -Our Jacobi processor employs design features that minimize the number of control clauses, e.g., the use of k-aligned CSR format precludes the need for muxes at the dot product tree input. Furthermore, unlike a GPP memory hierarchy, the HPRC memory organization does not penalize irregular memory accesses [24]. Therefore, on an FPGA, Jacobi appears to be primarily compute intensive.…”

Section: G Jacobi Design Considerationsmentioning

confidence: 99%

See 3 more Smart Citations

Mapping Floating-Point Kernels onto High Performance Reconfigurable Computers

Morris¹,

Abed²

2013

JCP

View full text Add to dashboard Cite

Contemporary field programmable gate arrays (FPGAs) combine the fine-grained design capability of the traditional lookup table with the speed of medium-scale and large-scale logic components such as RAM blocks or DSP blocks to provide for significant computational capability from a single FPGA. High performance reconfigurable computers, which typically use FPGAs as computational elements, have been commercially used to accelerate computational kernels. However, the deep pipelines and extensive parallelism needed for FPGAs to compete with GHz-scale general purpose processors make mapping of floating-point kernels a challenging research area. In this paper, we describe some of the progress that has been made towards solving some of these mapping challenges.

show abstract

Section: J Results 1) Description Of Test Problemsmentioning

confidence: 99%