Improving positive and negative bias illumination stress stability in parylene passivated IGZO transistors

Kiazadeh, Asal; Gomes, Henrique L.; Barquinha, Pedro; Martins, Jorge; Rovisco, Ana; Pinto, Joana; Martins, Rodrigo; Fortunato, Elvira

doi:10.1063/1.4960200

Cited by 65 publications

(42 citation statements)

References 22 publications

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“…Access to gate, source, and drain pads was opened using oxygen plasma in the Trion Phantom 3 system (Trion Technology, Inc., Clearwater, FL, USA). This passivation layer improves device stability, as shown in [ 14 , 15 ]. All the TFTs (isolated and integrated in circuits) had a channel length (L) of 20

m, with channel widths (W) in the range of 40 to 320

m. A cross-sectional view of the TFT structure is presented in the inset of Figure 1 b.…”

Section: Transistor and Circuit Fabrication And Characterizationmentioning

confidence: 90%

Bias Stress and Temperature Impact on InGaZnO TFTs and Circuits

et al. 2017

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This paper focuses on the analysis of InGaZnO thin-film transistors (TFTs) and circuits under the influence of different temperatures and bias stress, shedding light into their robustness when used in real-world applications. For temperature-dependent measurements, a temperature range of 15 to 85 °C was considered. In case of bias stress, both gate and drain bias were applied for 60 min. Though isolated transistors show a variation of drain current as high as 56% and 172% during bias voltage and temperature stress, the employed circuits were able to counteract it. Inverters and two-TFT current mirrors following simple circuit topologies showed a gain variation below 8%, while the improved robustness of a cascode current mirror design is proven by showing a gain variation less than 5%. The demonstration that the proper selection of TFT materials and circuit topologies results in robust operation of oxide electronics under different stress conditions and over a reasonable range of temperatures proves that the technology is suitable for applications such as smart food packaging and wearables.

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m, with channel widths (W) in the range of 40 to 320

m. A cross-sectional view of the TFT structure is presented in the inset of Figure 1 b.…”

Section: Transistor and Circuit Fabrication And Characterizationmentioning

confidence: 90%

Bias Stress and Temperature Impact on InGaZnO TFTs and Circuits

et al. 2017

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“…The caption inside the transfer plots reflects the order how measurements were made, with "+" and "−" denoting concave and convex bending of the devices, respectively. [47]. This degradation is nonrecoverable and presumably due to the fracture of the dielectric layer.…”

Section: Zto Tfts With Multicomponent/multilayer Ta-si-o Dielectric Omentioning

confidence: 99%

A Sustainable Approach to Flexible Electronics with Zinc‐Tin Oxide Thin‐Film Transistors

Fernandes

Santa

Santos

et al. 2018

Adv Elect Materials

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display backplanes and creating multifunctional flexible circuitry with thin-film technologies are considered. Within this scenario, amorphous oxide semiconductor (AOS) became one of the most competitive TFT technologies, enabling excellent uniformity in large areas, high transparency in visible spectrum, and field-effect mobility (µ FE ) exceeding 10 cm 2 V −1 s −1 even when fabricated below 200 °C. [1][2][3] The potential of these materials as semiconductors in TFTs started to be recognized in 2004 with the work by Nomura et al. on flexible indium-gallium-zinc oxide (IGZO) transistors. [4] Despite the establishment of IGZO TFTs as a key technology for large-area electronics, indium and gallium are critical raw materials, imposing important constrains regarding the sustainability of this approach. [5] Therefore, the ideal route for the next-generation AOS-based transistor technology should comprise an indium-and gallium-free semiconductor material, providing at least comparable performance and processing temperature to IGZO. Zinc-tin oxide (ZTO) has been recognized as a likely choice. Chiang et al. [6] reported in 2005 the first successful integration of sputtered ZTO as semiconductor layer in TFTs. Their staggered bottom-gate, top contact devices showed µ FE ≈ 20-50 cm 2 V −1 s −1 , turn-on voltage (V on ) between −5 and 5 V, and on/off ratio > 10 7 when annealed at 600 °C. However, µ FE drastically decreased to 5-15 cm 2 V −1 s −1 when lower annealing temperature (300 °C) was used, which is still too high for temperature-sensitive polymeric substrates as polyethylene naphthalene (PEN). Since then more than 150 articles on ZTO TFTs have been published, following both physical and solution-processing routes. Focusing on sputtering, which is the processing technique with easier penetration on an industrial TFT baseline process, aspects as different Zn:Sn ratios, [7][8][9] chamber pressure, oxygen flow ratio, and RF power during sputtering have been studied. [10] Nonetheless, for all these experiments a processing or post-processing temperature exceeding 300 °C was always used to achieve proper device operation (e.g., µ FE > 5 cm 2 V −1 s −1 in devices properly patterned, where overestimation of mobility due to fringing effects can be neglected. [11] A very recent work by Han et al. [12] is the exception to this, where a remarkable saturation mobility (µ sat ) of 67 cm 2 V −1 s −1 is achieved for polycrystalline tin-doped Zinc-tin oxide (ZTO) is widely invoked as a promising indium and galliumfree alternative for amorphous oxide semiconductor based thin-film transistors (TFTs). The main bottleneck of this semiconductor material compared to mainstream indium-gallium-zinc oxide (IGZO) is centered in the larger processing temperatures required to achieve acceptable performance (>300 °C), not compatible with low-cost flexible substrates. This work reports for the first time flexible amorphous-ZTO TFTs processed at a maximum temperature of 180 °C. Different aspects are explored to obtain performance levels comparable ...

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“…These materials, with the most prominent representative being indium-gallium-zinc oxide (IGZO), [1][2][3] are generally transparent for visible light, amorphous, and processable at relatively low temperatures (compared to silicon). These materials, with the most prominent representative being indium-gallium-zinc oxide (IGZO), [1][2][3] are generally transparent for visible light, amorphous, and processable at relatively low temperatures (compared to silicon).…”

Section: Introductionmentioning

confidence: 99%

2D Resistive Switching Based on Amorphous Zinc–Tin Oxide Schottky Diodes

Branca

Deuermeier

Martins

et al. 2019

Adv Elect Materials

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of less destructive switching events, since the device reliability is independent of the reproducibility of the filament formation. [6] Frequently, an analog switching is observed, which is applicable for neuromorphic systems. [7][8][9][10] Reports exist in the literature, which explore area-dependent switching involving the homogeneous migration of defects or ions through the thickness of the switching matrix. [11,12] This can be referred to as 3D RS. In a device with asymmetric electrodes, both 1D RS and 3D RS result in counter eightwise (c8w) switching loops, when the bias is applied to the current blocking electrode. [13] Another type of area-dependent RS exists when ions are exchanged (or trapping occurs at the interface) between the switching matrix and the electrode. If the current transport through this interface is modulated as a consequence of the ion exchange/trapping, then this can be referred to as 2D RS. The direction of the switching loops is opposite to 1D RS and 3D RS, that is, eightwise (8w) when the bias is applied to the current blocking electrode. Frequently, 2D volatile switching has been observed as a secondary process, affecting the high resistive state (HRS) of an otherwise 1D RS device. [14][15][16][17] In addition, the choice between digital and analog operation modes by different device initialization schemes has been reported for NiO-based devices. [18] However, the resistance window for the analog mode was below one order of magnitude and the mechanism was discussed as 3D RS.Both in 3D RS and 2D RS, the active interface represents a barrier to the current flow, for example, a Schottky junction. [19] In the case of Ti/Pr 0.7 Ca 0.3 MnO 3 (PCMO) devices the underlying mechanism is based on a redox reaction between the titanium oxide interlayer and the PCMO. [20,21] In oxide-based devices with a platinum Schottky barrier bottom electrode, electronic trapping at interface states was proposed as a mechanism. [15] To allow a sizeable data retention, structural stabilization of the trapped charge needs to occur. [22] To achieve a high ratio between HRS and low resistance state (LRS) in 3D and 2D RS, a highly mobile Fermi level, that is, a highly variable charge carrier concentration is desirable. In thin-film transistors (TFT), AOS are known to yield tremendously high on/off ratios. [23] Diodes of AOS have rectification ratios of 10 6 . [24] These applications show how the material is able to change from an insulator to a metallic conductor by A room-temperature-processed resistive switching Schottky diode that can be operated in two distinct modes, depending solely on the choice of device initialization mode, is presented. Electroforming in the diode's reverse polarity leads to an abrupt filamentary switching with inherently long data retention at the expense of rectification. After this electroforming process, the devices may work in either a bipolar or unipolar manner with a resistance window of at least two orders of magnitude. Device initialization in the forward direction shows a smoo...

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Improving positive and negative bias illumination stress stability in parylene passivated IGZO transistors

Cited by 65 publications

References 22 publications

Bias Stress and Temperature Impact on InGaZnO TFTs and Circuits

Bias Stress and Temperature Impact on InGaZnO TFTs and Circuits

A Sustainable Approach to Flexible Electronics with Zinc‐Tin Oxide Thin‐Film Transistors

2D Resistive Switching Based on Amorphous Zinc–Tin Oxide Schottky Diodes

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