Improving processor efficiency by statically pipelining instructions

Abstract

A new generation of applications requires reduced power consumption without sacrificing performance. Instruction pipelining is commonly used to meet application performance requirements, but some implementation aspects of pipelining are inefficient with respect to energy usage. We propose static pipelining as a new instruction set architecture to enable more efficient instruction flow through the pipeline, which is accomplished by exposing the pipeline structure to the compiler. While this approach simplifies hardware pipeline requirements, significant modifications to the compiler are required. This paper describes the code generation and compiler optimizations we implemented to exploit the features of this architecture. We show that we can achieve performance and code size improvements despite a very low-level instruction representation. We also demonstrate that static pipelining of instructions reduces energy usage by simplifying hardware, avoiding many unnecessary operations, and allowing the compiler to perform optimizations that are not possible on traditional architectures.

Optimizing Transfers of Control in the Static Pipeline Architecture

“…In a prior version of the SP datapath [7], only one other target address calculation was hoisted out of loops into a dedicated internal TARG register, which is no longer supported in the SP datapath. The compiler now hoists these target address calculations out of the loop when an integer register is available, which can reduce both execution time (because there are fewer effects to schedule) and energy usage.…”

Optimizing Transfers of Control in the Static Pipeline Architecture

“…The SP pipeline in our previous simulations consisted of two stages, instruction fetch (IF) and execute (EX), where decoding instructions was assumed to be part of the EX stage [7]. In order to make the clock period comparable to a baseline MIPS processor in a new SP VHDL implementation, we added an instruction decode (ID) stage between the IF and EX stages in which the instructions are converted into control signals.…”

Software-controlled processor stalls for time and energy efficient data locality optimization

“…In other situations, transforming the code to execute within a power budget and save energy, may harm performance. Significant efforts have been made to achieve a better balance between the two [15], [11], [7], [14], [8], [6], [5], [9]. Dynamic Voltage and Frequency Scaling (DVFS) is a common technique for saving energy, by scaling down voltage and frequency.…”

“…Apart from DVFS techniques, other proposals target compiler-architecture collaborations, which enable a wiser use of the micro-architecture based on static information [6], [5], [16]. In particular, Finlayson et al [6], [5] focus on improving the processor pipeline and propose an entirely statically pipelined processor, relying on an optimizing compiler to insert control information for each instruction.…”

“…In particular, Finlayson et al [6], [5] focus on improving the processor pipeline and propose an entirely statically pipelined processor, relying on an optimizing compiler to insert control information for each instruction. Thus, redundant operations performed by traditional processor pipelines are eliminated (e.g., unnecessary register reads and writes, when their consumers retrieve such information from forwarding).…”