Improving Program Efficiency by Packing Instructions into Registers

Hines, Stephen; Green, J.; Tyson, Gary; Whalley, David

doi:10.1109/isca.2005.32

Cited by 26 publications

(50 citation statements)

References 17 publications

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“…al. [12] present a technique for reducing program size, power consumption and execution time by storing commonly used instructions in an instruction register file. They allow instructions to reference multiple entries in the instruction register file.…”

Section: Compilationmentioning

confidence: 99%

Improving processor efficiency by statically pipelining instructions

Finlayson¹,

Davis²,

Gavin³

et al. 2013

Proceedings of the 14th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems

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Section: Compilationmentioning

confidence: 99%

Improving processor efficiency by statically pipelining instructions

Finlayson¹,

Davis²,

Gavin³

et al. 2013

Proceedings of the 14th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems

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“…However, in the memory format instructions, the displacement field has to be shortened and uses encoded into the new free space. Although this implementation is specific to the Alpha, other researchers have found that free bits are common in other ISAs, such as MIPS [Hines et al 2005].…”

Section: Isa Impactmentioning

confidence: 99%

Energy-efficient register caching with compiler assistance

Jones

O’Boyle

Abella

et al. 2009

ACM Trans. Archit. Code Optim.

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The register file is a critical component in a modern superscalar processor. It must be large enough to accommodate the results of all in-flight instructions. It must also have enough ports to allow simultaneous issue and writeback of many values each cycle. However, this makes it one of the most energy-consuming structures within the processor with a high access latency. As technology scales, there comes a point where register accesses are the bottleneck to performance and so must be pipelined over several cycles. This increases the pipeline depth, lowering performance.To overcome these challenges, we propose a novel use of compiler analysis to aid register caching. Adding a register cache allows us to preserve single-cycle register accesses, maintaining performance and reducing energy consumption. We do this by passing information to the processor using free bits in a real ISA, allowing us to cache only the most important registers. Evaluating the register cache over a variety of sizes and associativities and varying the read ports into the cache, our best scheme achieves an energy-delay-squared (EDD) product of 0.81, with a performance increase of 11%. Another configuration saves 13% of register system energy. Using four register cache read ports brings both performance gains and energy savings, consistently outperforming two state-of-the-art hardware approaches.

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“…Our initial strategy for selecting instructions to reside in the IRF was to simply choose the most frequently accessed instructions [1]. We now distinguish instructions by howm anyo ft he fiveR ISA slots are consumed.…”

Section: Progress and Outcomesmentioning

confidence: 99%

“…While a compiler optimization and/or an architectural feature may be developed to improve one design goal of a processor,i to ften comes at the detriment of another.A n instruction register file (IRF), unlikemost architectural and compiler enhancements, has been shown to simultaneously reduce power requirements, decrease code size, and improve performance [1]. This paper describes the progress and outcomes of the NSF Grant CNS-0615085, whose main goal is to enhance the effectiveness of utilizing an IRF.W ea lso introduce a tagless hit instruction cache (IC) that reduces energy consumption without increasing execution time by guaranteeing hits in this small IC.…”

Section: Introductionmentioning

confidence: 99%