A many-core based co-processor, such as the Intel Many Integrated Core (MIC) Architecture, connected to a serverlevel multi-core host processor via a PCI Express bus, has recently been the subject of a great deal of attention. In such a machine, because the many-core is separated from the host processor with disk I/O and it also has limited cache and memory bandwidth, performance degradation can results from cache pollution and data transfer latency caused by processing file operations.