Improving the performance of E-beam 2nd writing in mask alignment accuracy and pattern faultless for CPL technology

Lee, Booky; Hung, Richard Yu Yuan; Lin, Orson; Wu, Yuan-Hsun; Kozuma, Makoto; Shih, Chiang-Lin; Hsu, Michael; Hsu, Stephen

doi:10.1117/12.576542

SPIE Proceedings

2005

DOI: 10.1117/12.576542

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Improving the performance of E-beam 2nd writing in mask alignment accuracy and pattern faultless for CPL technology

Booky Lee

Richard Yu Yuan Hung

Orson Lin

et al.

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“…From previous study, the 2 nd level writing by E-Beam writer has been developed to ensure the manufacturability of CPL process [1]. To fulfill the application of CPL Mask, we implemented this technology for 65nm DRAM patterning.…”

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Application of CPL mask for whole chip 65nm DRAM patterning

et al. 2005

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To extend the application of ArF exposure tool, CPL is one of the most powerful technologies for the resolution enhancement. From previous study, the 2 nd level writing by E-Beam writer has been developed to ensure the manufacturability of CPL process [1]. To fulfill the application of CPL Mask, we implemented this technology for 65nm DRAM patterning. First we studied the performance and characteristics of CPL mask with optimized exposure illumination setting for the desired pattern and dimension of 65nm DRAM. Then the mask data for CPL mask manufacture has been generated by modeled pattern decomposition approach together with rule and modeled OPC. This was accomplished by using an engine named MaskWeaver TM . For the manufacture of CPL mask, we used a binary mask and the Qz was etched for the 180 degrees phase difference. We utilized a 2 nd level writing by an E-Beam writer to make the zebra pattern that was generated by the engine for the optimized patterning performance. The exposure tool we utilized for the verification of wafer patterning is an advanced 193nm exposure system. The process performance indexes such as MEEF, process window, CD uniformity were collected to show the capability of CPL process. Also, simulation and empirical data were compared to verify the performance of CPL technology. So by using an optimized CPL technology included mask data generation skill, mask making specifications, and ArF illumination optimization, we can meet the manufacture requirement of 65nm DRAM.

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Application of CPL mask for whole chip 65nm DRAM patterning

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Improving the performance of E-beam 2nd writing in mask alignment accuracy and pattern faultless for CPL technology

Cited by 1 publication

References 0 publications

Application of CPL mask for whole chip 65nm DRAM patterning

Application of CPL mask for whole chip 65nm DRAM patterning

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